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Improving the scalability of SAMBA bus architecture

Published: 18 January 2005 Publication History

Abstract

SAMBA bus [1] is a high performance bus architecture that can deliver multiple transactions in one bus cycle under single-winner bus arbitration. The bus architecture displays several advantages such as, high bandwidth, low latency, and low performance penalty from arbitration delay, all of which make it more scalable than traditional buses. However, its scalability may be limited by the bus access logic delay. As a module is connected to the bus through its interface unit, which is connected in series on the bus, the bus logic delay increases linearly as the bus size increases. In this paper, we propose to increase the scalability of SAMBA buses through two methods: control signal lookahead and module clustering. The control signal lookahead technique can determine the bus access control signal in advance, thereby reducing the effective delay of each interface unit. Module clustering, on the other hand, can reduce the number of interface units attached to a bus. Experimental results show that combining these two methods can effectively reduce the bus logic delay, and thus increase the scalability of SAMBA buses.

References

[1]
R. Lu and C.-K. Koh. SAMBA-Bus, a high performance bus architecture for System-on-Chips. In Proc. Int. Conf. on Computer Aided Design, 2003.
[2]
IBM. CoreConnect Bus Architecture, 1999.
[3]
ARM, Limited. AMBA Specification, 1999.
[4]
Sonics, Inc. Open Core Protocol Specification, 1999.
[5]
E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen. Overview of bus-based system-on-chip interconnections. In Proc. IEEE Int. Symp. on Circuits and Systems, pages II--372 -- II--375, 2002.
[6]
R. Lu and C.-K. Koh. A high performance bus communication architecture through bus splitting. In Proc. Asia South Pacific Design Automation Conf., pages 751--755, 2004.
[7]
K. Lahiri, A. Raghunathan, and G. Lakshminarayana. LOTTERYBUS: A new high-performance communication architecture for System-on-Chip designs. In Proc. Design Automation Conf, 2001.
[8]
C. Hsieh and M. Pedram. Architectural energy optimization by bus splitting. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21:408--414, April 2002.

Cited By

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  • (2010)An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitrationACM Transactions on Embedded Computing Systems (TECS)10.1145/1721695.17217019:4(1-39)Online publication date: 6-Apr-2010

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
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Publication History

Published: 18 January 2005

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View all
  • (2010)An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitrationACM Transactions on Embedded Computing Systems (TECS)10.1145/1721695.17217019:4(1-39)Online publication date: 6-Apr-2010

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