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Register placement for low power clock network

Published: 18 January 2005 Publication History

Abstract

In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

References

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  • (2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685949(1-7)Online publication date: 9-Sep-2024
  • (2023)Emergence of Cutting-Edge Technologies on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_10(251-277)Online publication date: 23-Sep-2023
  • (2016)Clock-Tree-Aware Incremental Timing-Driven PlacementACM Transactions on Design Automation of Electronic Systems10.1145/285879321:3(1-27)Online publication date: 19-Apr-2016
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  1. Register placement for low power clock network

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    cover image ACM Conferences
    ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
    January 2005
    1495 pages
    ISBN:0780387376
    DOI:10.1145/1120725
    • General Chair:
    • Ting-Ao Tang
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 January 2005

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    View all
    • (2024)Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685949(1-7)Online publication date: 9-Sep-2024
    • (2023)Emergence of Cutting-Edge Technologies on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_10(251-277)Online publication date: 23-Sep-2023
    • (2016)Clock-Tree-Aware Incremental Timing-Driven PlacementACM Transactions on Design Automation of Electronic Systems10.1145/285879321:3(1-27)Online publication date: 19-Apr-2016
    • (2015)Register Clustering Methodology for Low Power Clock Tree SynthesisJournal of Computer Science and Technology10.1007/s11390-015-1531-430:2(391-403)Online publication date: 13-Mar-2015
    • (2009)Register placement for high-performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874972(1470-1475)Online publication date: 20-Apr-2009
    • (2009)Multi-domain clock skew scheduling-aware register placement to optimize clock distribution networkProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874824(833-838)Online publication date: 20-Apr-2009

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