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Skew scheduling and clock routing for improved tolerance to process variations

Published: 18 January 2005 Publication History

Abstract

The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock tree design algorithm which is driven by the tolerance towards process variations. We consider tolerance to process variation in various stages of clock tree synthesis which include clock skew scheduling, abstract tree generation and layout embedding. The primary objective of this work is to minimize the maximum skew violation and a layout embedding technique specifically targeting this objective is detailed. Experimental results indicate the our proposed procedure leads to significant reduction in maximum skew violation due to process variation with negligible change in wire length.

References

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Cited By

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  • (2013)A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process VariationsIEICE Transactions on Information and Systems10.1587/transinf.E96.D.1980E96.D:9(1980-1985)Online publication date: 2013
  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2011)A complete framework of simultaneous functional unit and register binding with skew scheduling2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770724(1-7)Online publication date: Mar-2011
  • Show More Cited By

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 January 2005

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Author Tags

  1. clock routing
  2. layout embedding
  3. process variation
  4. reliability
  5. skew scheduling

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Cited By

View all
  • (2013)A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process VariationsIEICE Transactions on Information and Systems10.1587/transinf.E96.D.1980E96.D:9(1980-1985)Online publication date: 2013
  • (2013)Revisiting automated physical synthesis of high-performance clock networksACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210218:2(1-27)Online publication date: 11-Apr-2013
  • (2011)A complete framework of simultaneous functional unit and register binding with skew scheduling2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770724(1-7)Online publication date: Mar-2011
  • (2009)Multi-domain clock skew scheduling-aware register placement to optimize clock distribution networkProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874824(833-838)Online publication date: 20-Apr-2009
  • (2009)Clock buffer polarity assignment for power noise reductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200918717:6(770-780)Online publication date: 1-Jun-2009
  • (2007)Physical aware clock skew reschedulingProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228896(473-476)Online publication date: 11-Mar-2007
  • (2006)Statistical clock tree routing for robustness to process variationsProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123037(149-156)Online publication date: 9-Apr-2006

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