Article

A new register file access architecture for software pipelining in VLIW processors

Authors:

Yanjun Zhang,

Hu he,

Yihe SunAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 627 - 630

https://doi.org/10.1145/1120725.1120979

Published: 18 January 2005 Publication History

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Abstract

This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.

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Voitsechov DZulfiqar AStephenson MGebhart MKeckler S(2018)Software-Directed Techniques for Improved GPU Register File UtilizationACM Transactions on Architecture and Code Optimization10.1145/324390515:3(1-23)Online publication date: 24-Sep-2018
https://dl.acm.org/doi/10.1145/3243905
He HYang XZhang Y(2017)On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System UsageThe Computer Journal10.1093/comjnl/bxx001Online publication date: 22-Jan-2017
https://doi.org/10.1093/comjnl/bxx001
Xiao JLi WShen X(2014)A low-power register file based on access queues for multi-issue processors2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS)10.1109/ICIS.2014.6912113(87-92)Online publication date: Jun-2014
https://doi.org/10.1109/ICIS.2014.6912113
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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Voitsechov DZulfiqar AStephenson MGebhart MKeckler S(2018)Software-Directed Techniques for Improved GPU Register File UtilizationACM Transactions on Architecture and Code Optimization10.1145/324390515:3(1-23)Online publication date: 24-Sep-2018
https://dl.acm.org/doi/10.1145/3243905
He HYang XZhang Y(2017)On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System UsageThe Computer Journal10.1093/comjnl/bxx001Online publication date: 22-Jan-2017
https://doi.org/10.1093/comjnl/bxx001
Xiao JLi WShen X(2014)A low-power register file based on access queues for multi-issue processors2014 IEEE/ACIS 13th International Conference on Computer and Information Science (ICIS)10.1109/ICIS.2014.6912113(87-92)Online publication date: Jun-2014
https://doi.org/10.1109/ICIS.2014.6912113
Tang HYang XWang SZhang Y(2013)Optimizing Instruction Scheduling and Register Allocation for Register‐File‐Connected Clustered VLIW ArchitecturesThe Scientific World Journal10.1155/2013/9130382013:1Online publication date: 18-Jul-2013
https://doi.org/10.1155/2013/913038
Gebhart MJohnson DTarjan DKeckler SDally WLindholm ESkadron K(2012)A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput ProcessorsACM Transactions on Computer Systems10.1145/2166879.216688230:2(1-38)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2166879.2166882
Gebhart MKeckler SDally WGaluzzi CCarro LMoshovos APrvulovic M(2011)A compile-time managed multi-level register file hierarchyProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155675(465-476)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155675
Payá-Vayá GMartín-Langerwerf JPirsch P(2010)A Multi-Shared Register File Structure for VLIW ProcessorsJournal of Signal Processing Systems10.1007/s11265-009-0355-258:2(215-231)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1007/s11265-009-0355-2
Hsu JWu YLin XChung Y(2007)SCRFProceedings of the 9th international conference on Parallel Computing Technologies10.5555/2392094.2392151(525-536)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.5555/2392094.2392151
Shen ZHe HZhang YSun Y(2007)A video specific instruction set architecture for ASIP designVLSI Design10.1155/2007/584312007:2(1-7)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1155/2007/58431
Hsu JWu YLin XChung Y(2007)SCRF – A Hybrid Register File ArchitectureParallel Computing Technologies10.1007/978-3-540-73940-1_52(525-536)Online publication date: 2007
https://doi.org/10.1007/978-3-540-73940-1_52

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Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Software and hardware techniques to optimize register file utilization in VLIW architectures

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