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A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

Published: 18 January 2005 Publication History

Abstract

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18μm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

References

[1]
J. Zerbe, et al., "Equalization and clock recovery for a 2.5-10Gbs 2-PAM/4-PAM backplane transceiver cell," J. Solid-State Circuits, vol. 38, pp. 2121--2130, Dec. 2003.
[2]
C-H Lin, C-H Wang, and S-J Jou, "5 Gb/s serial link transmitter with pre-emphasis", Proc. ASP-DAC 2003, pp. 795--800, Jan. 2003.
[3]
R. Farjad-Rad, C.-K.K. Yang, M. A. Horowitz, and T. H. Lee, "A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter", J. Solid-State Circuits, vol. 34, pp. 580--585, May 1999.
[4]
M. Li, S. Wang, Y. Tao, and T. Kwasniewski, "FIR Filter Optimization as Pre-Emphasis of High-Speed Backplane Data Transmission", Electronics Letters, vol. 40, pp. 912--913, July 2004.
[5]
J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector", J. Solid-state Circuits, vol. 38, pp. 13--21, Jan. 2003.
[6]
K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, and M. Yotsuyanagi, "A CMOS 50% duty cycle repeater using complementary phase blending", VLSI Circuits Symp., pp. 48--49, June 2000.
[7]
T. Gawa and K. Taniguchi, "A 50% duty-cycle correction circuit for PLL output", Proc. ISCAS 2002, pp. IV-21-IV-24, May 2002.

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  • (2024)Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and ChallengesSystems Engineering - Design, Analysis, Programming, and Maintenance of Complex Systems10.5772/intechopen.1004105Online publication date: 31-Jul-2024
  • (2012)A 2.4 Gbps transmitter with programmable de-emphasis scheme for DDR3 memory interface2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)10.1109/ICIAS.2012.6306106(713-718)Online publication date: Jun-2012
  • (2011)Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18μm CMOSMicroelectronics Journal10.1016/j.mejo.2011.08.00342:11(1216-1224)Online publication date: Nov-2011
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  1. A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

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    cover image ACM Conferences
    ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
    January 2005
    1495 pages
    ISBN:0780387376
    DOI:10.1145/1120725
    • General Chair:
    • Ting-Ao Tang
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 18 January 2005

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    View all
    • (2024)Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and ChallengesSystems Engineering - Design, Analysis, Programming, and Maintenance of Complex Systems10.5772/intechopen.1004105Online publication date: 31-Jul-2024
    • (2012)A 2.4 Gbps transmitter with programmable de-emphasis scheme for DDR3 memory interface2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012)10.1109/ICIAS.2012.6306106(713-718)Online publication date: Jun-2012
    • (2011)Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18μm CMOSMicroelectronics Journal10.1016/j.mejo.2011.08.00342:11(1216-1224)Online publication date: Nov-2011
    • (2010)Optimal equalization for reducing the impact of channel group delay distortion on high-speed backplane data transmissionAEU - International Journal of Electronics and Communications10.1016/j.aeue.2009.04.01064:7(671-681)Online publication date: Jul-2010
    • (2009)A low switching time transmitter for high speed adaptive pre-emphasis serial links2009 International Semiconductor Conference10.1109/SMICND.2009.5336672(481-484)Online publication date: Oct-2009
    • (2009)Analysis of adaptive FIR filter pre-emphasis for high speed serial linksAFRICON 200910.1109/AFRCON.2009.5308166(1-5)Online publication date: Sep-2009
    • (2009)FIR filter optimization using bit-edge equalization in high-speed backplane data transmissionMicroelectronics Journal10.1016/j.mejo.2009.06.00340:10(1449-1457)Online publication date: Oct-2009
    • (2008)ISI mitigation using bit-edge equalization in high-speed backplane data transmission2008 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2008.4657842(589-593)Online publication date: May-2008
    • (2008)Ultra wideband wireless serial data communication at 10Gb/s in CMOS 90nm2008 IEEE-EPEP Electrical Performance of Electronic Packaging10.1109/EPEP.2008.4675896(135-138)Online publication date: Oct-2008
    • (2008)Using bit-edge equalization in highspeed backplane data transmission2008 Third International Conference on Communications and Networking in China10.1109/CHINACOM.2008.4685108(642-646)Online publication date: Aug-2008

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