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Partitioned bus coding for energy reduction
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Source with EDA Technofair Design Automation Conference Asia and South Pacific archive
Proceedings of the 2005 conference on Asia South Pacific design automation table of contents
Shanghai, China
SESSION: Poster session IV table of contents
Pages: 1280 - 1283  
Year of Publication: 2005
ISBN:0-7803-8737-6
Authors
Lin Xie  Zhejiang University
Peiliang Qiu  Zhejiang University
Qinru Qiu  State University of New York, Binghamton, New York
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: Shanghai IC Industry Association
: IEEE SSCS Shanghai Chapter
: IEEE CAS
: IEEE Beijing Section
: Fudan University
: Chinese Institute of Electronics
Publisher
ACM  New York, NY, USA
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ABSTRACT

For VLSI design in deep submicron technology, the bus energy reduction has become more and more important. This paper studies the bus partition scheme for the Transition Pattern Coding (TPC). The genetic algorithm based approach is used. A closed-form expression is derived to calculate the energy dissipation for the partitioned bus with TPC coding. A general bus model with coupling capacitance is considered during the energy estimation and optimization. The resulted partitioned bus coding reduces the encoding and decoding complexity of the original TPC. The experimental results show that the TPC with careful bus partitioned saves up to 16.9% the energy of the TPC with random bus partition.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Y. Shin, S. Chae and K. Choi, "Reduction of bus-transitions with partial bus-invert coding," IEE Electronics Letters, vol.34, pp.642-643, 1998
 
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S. Hong, T. Kim, U. Narayanan and K. S. Chung, "Decomposition of bus-invert coding for low power I/O," J. Circuits, Syst., Comput., vol. 10, pp. 101-111, 2000
 
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P. Sotiriadis and A. Chandrakasan, "Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model," IEEE Trans. on Circuits and Systems -I: Fundamental Theory and Application, vol. 50, pp. 1280-1295, October 2003
 
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C. Lyuh, T. Kim, and K. Kim, "Coupling-Aware High-Level Interconnect Synthesis," IEEE Trans. on Computer-Aided Design, vol. 23, pp. 157-164, January, 2004

Collaborative Colleagues:
Lin Xie: colleagues
Peiliang Qiu: colleagues
Qinru Qiu: colleagues