High speed differential pulse-width control loop based on frequency-to-voltage converters

ABSTRACT

A novel differential pulse-width control loop circuit based on high speed frequency-to-voltage converters is proposed. To demonstrate its functionality, a circuit has been designed and simulated in 0.18mm CMOS technology. Results show that the proposed circuit can correct a clock signal's duty cycle even for frequencies as high as 5 GHz. This design can be used to correct clock signal distortion due to process variations in high speed applications such as half-rate clock and data recovery systems.

REFERENCES

• 1: U.-R. Cho et al., A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM, Journal of Solid-State Circuits, Vol. 38, No. 11, Nov. 2003, pp. 1943--1951.
• 2: J. Savoj, B. Razavi, A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector, Journal of Solid-State Circuits, Vol. 36, No. 5, May 2001, pp. 761--768.
• 3: Nikola Nedovic , Vojin G. Oklobdzija, Dual-edge triggered storage elements and clocking strategy for low-power systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.577-590, May 2005 [doi>10.1109/TVLSI.2005.844302]
• 4: W.-M. Lin, H.-Y. Huang, A Low-Jitter Mutual-Correlated Pulsewidth Control loop Circuit, Journal of Solid-State Circuits, Vol. 39, No. 8, Aug. 2004, pp. 1366--1369.
• 5: F. Mu, Member, C. Svensson, Pulsewidth Control Loop in High-Speed CMOS Clock Buffers, Journal of Solid-State Circuits, Vol. 35, No. 2, Feb. 2000, pp. 134--141.
• 6: J. S. Wang and P. H. Yang, Low-Voltage CMOS Pulsewidth Control Loop Using Push-Pull Charge Pump, Electronics Letters, 29th Mar. 2001 Vol. 37 No. 7 pp. 409--411.
• 7: H. T. Bui, Y. Savaria, High-Speed Differential Frequency-to-Voltage Converter, Northeast Workshop on Circuits and Systems, Jun. 2005, pp. 76--79.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Input/output circuits

General Terms:
Design, Performance

Keywords:
PWCL, duty cycle, frequency-to-voltage, high-speed