An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques

ABSTRACT

We evaluate the effectiveness of dual-V_t design in the presence of both subthreshold leakage and leakage due to gate oxide tunneling. At the device level, we use detailed HSPICE simulation to investigate the total leakage impact of three methods of dual-V_t implementation: multiple channel doping, channel length, and oxide thickness. At the system level, we generate and characterize a standard cell library and apply three representative delay-constrained leakage minimization dual-V_t assignment algorithms to the ISCAS'85 combinational benchmark circuits. Results show that oxide thickness modulation effectively reduces total leakage power consumption, but channel doping and channel length modulation are less effective.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration); Advanced technologies

General Terms:
Algorithms, Design, Performance

Keywords:
dual threshold voltage, gate oxide tunneling, low power circuit design, subthreshold leakage