General transistor-level methodology on VLSI low-power design

ABSTRACT

In this work, we modify the Alpha-Power Law to accurately simulate BSIM3-70nm gate delay on transistor level. Combined with efficient power analysis methods, we develop one transistor-level simulator to efficient estimate performance and power for CMOS gates consisting of heterogeneous transistors. Furthermore, we propose a novel transistor-level optimization engine consisting of two-step algorithms. The former gate-space algorithm uses the clustering strategy to cut down algorithm complexity. The latter transistor-space algorithm employs fine granularity to pursue reducing more power consumption. Experiments show the following advantages: 1. Our transistor-level simulator takes average 1.0ms (on an ordinary PM1.4G-256M laptop computer) to analyze one gate and can accurately estimate circuit delay with only 2-7% worst-case error. 2. Our methodology is so general that it can analyze and optimize heterogeneous circuit in which each transistor may have its own different V_T0, channel width and length. 3. In the transistor-level width+V_T0+length-sized optimization, our engine takes feasible running time (856.4s for C7552) to cut down 22.58%(average) and 43.02%(maximum) leakage power caused by gate-level optimum solution nearly without penalty of active power.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
nanometer, optimization, simulation, transistor level