Delay and peak power minimization for on-chip buses using temporal redundancy

ABSTRACT

In this paper, we propose a novel temporal redundancy based encoding technique for delay and peak power minimization. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks for 90nm and 65nm technologies. The experimental results show that our approach is very effective in reducing the peak power. From the delay perspective, our approach reduces the delay by at least 11% (4%) in the address (data) buses compared to the data transmission without encoding.

REFERENCES

• 1: Berkeley predictive technology model. http://www-device.eecs.berkeley.edu/~ptm/interconnect.html
• 2: SimpleScalar Toolset. http://www.simplescalar.com.
• 3: SPEC CPU2000 Benchmark. http://www.spec.org
• 4: International Technology Roadmap for Semiconductors, 2001. http://public.itrs.net
• 5: Ravishankar Arunachalam , Emrah Acar , Sani R. Nassif, Optimal shielding/spacing metrics for low power design, Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), p.167, February 20-21, 2003
• 6: F. Caignet et al. "The Challenge of Signal Integrity in Deep-submicrometer CMOS Technology". IEEE, 89(4), 2001, pp. 556--573.
• 7: Chunjie Duan , Anup Tirumala, Analysis and Avoidance of Cross-Talk in On-Chip Buses, Proceedings of the The Ninth Symposium on High Performance Interconnects (HOTI '01), p.133, August 22-24, 2001
• 8: Ki Wook Kim , Kwang Hyun Baek , Naresh Shanbhag , C. L. Liu , Sung Mo Kang, Coupling-driven signal encoding scheme for low-power interface design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 9: Lin Li , N. Vijaykrishnan , Mahmut Kandemir , Mary Jane Irwin, A Crosstalk Aware Interconnect with Variable Cycle Transmission, Proceedings of the conference on Design, automation and test in Europe, p.10102, February 16-20, 2004
• 10: C.-G. Lyuh et al. "Low Power Bus Encoding with Crosstalk Delay Elimination". In ASIC/SOC, 2002, pp. 389--393.
• 11: Madhu Mutyam , Melvin Eze , N. Vijaykrishnan , Yuan Xie, Delay and Energy Efficient Data Transmission for On-Chip Buses, Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, p.355, March 02-03, 2006 [doi>10.1109/ISVLSI.2006.33]
• 12: P. Sotiriadis et al. "Low Power Bus Coding Techniques Considering Inter-wire Capacitances". In CICC, 2000, pp. 507--510.
• 13: Paul P. Sotiriadis , Anantha Chandrakasan, Reducing bus delay in submicron technology using coding, Proceedings of the 2001 conference on Asia South Pacific design automation, p.109-114, January 2001, Yokohama, Japan [doi>10.1145/370155.370294]
• 14: Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002 [doi>10.1109/TVLSI.2002.1043337 ]
• 15: Srinivasa R. Sridhara , Arshad Ahmed , Naresh R. Shanbhag, Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.12-17, October 11-13, 2004
• 16: D. Sylvester et al. "Analytical Modeling and Characterization of Deep-submicrometer Interconnect". IEEE, 89(5), 2001, pp. 634--664.
• 17: Bret Victor , Kurt Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 18: Joon-Seo Yim , Chong-Min Kyung, Reducing cross-coupling among interconnect wires in deep-submicron datapath design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.485-490, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309984]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

General Terms:
Design, Performance

Keywords:
coding, crosstalk, low-power