Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series

ABSTRACT

Analysis of nonlinearity in inductively source degenerated (ISD) CMOS LNA's Using Volterra series is presented. The effects of cascode transistor, parasitic capacitances in cascode node and output load are considered in this paper. In comparison to other works, this work completely follows the HSPICE simulation results. Second order nonlinearity analysis; which is more important in low IF and zero IF receivers, is done for the first time in ISD CMOS LNA in this paper. Simple relations are obtained for IIP2 and IIP3 of the circuit which can be helpful for the RF designers and have great agreement with HSPICE simulation results. For verifying the relations, a LNA is designed and simulated with HSPICE using a 0.35 μm CMOS technology for a prototype GSM receiver. The HSPICE simulation results show 19.7 dB voltage gain, 6.5 dBm IIP₃ and 23.8 dBm IIP₂, while the analytical relations predict 19.4 dB voltage gain, 7.6 dBm IIP₃ and 25.3 dBm IIP₂.

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INDEX TERMS

Primary Classification:
  F. Theory of Computation

General Terms:
Design, Theory

Keywords:
CMOS LNA, cascode, distortion, inductively source degenerated (ISD), intermodulation (IM), linearity, second order interception point (IIP₂), third order interception point (IIP₃), volterra kernels, volterra series