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On finding the minimum test set of a BDD-based circuit
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 16th ACM Great Lakes symposium on VLSI table of contents
Philadelphia, PA, USA
POSTER SESSION: Poster session 1 table of contents
Pages: 169 - 172  
Year of Publication: 2006
ISBN:1-59593-347-6
Authors
Gopal Paul  Indian Institute of Technology, Kharagpur, India
Ajit Pal  Indian Institute of Technology, Kharagpur, India
Bhargab B. Bhattacharya  Indian Statistical Institute, Kolkata, India
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

The Binary Decision Diagram (BDD) is a powerful vehicle for large-scale functional specification and circuit design. In this paper, we consider the open problem of generating in polynomial time, the exact minimum set (T) of test vectors for detecting all single stuck-at faults in such a BDD-based circuit synthesized with multiplexors. It is shown that for a single-output circuit, T = 2k, where k is the minimum number of paths that cover all the arcs of the BDD graph. The value of k, and consequently the test set T, can be readily determined by running the max-flow algorithm on a network derived from the BDD, followed by a simple graph traversal. This procedure not only generates the optimal test set in polynomial time, but also obviates the need of employing an ATPG (Automatic Test Pattern Generator) and a fault simulator. For multi-output circuits, the procedure requires slight enhancement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Gopal Paul: colleagues
Ajit Pal: colleagues
Bhargab B. Bhattacharya: colleagues