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ABSTRACT
To compensate for the growing effect of process, temperature and voltage variations in digital ICs, several dynamic approaches have been proposed. These approaches require the use of capacitors to offset the effects of variations. Although MOSFET based capacitors are a natural choice, such capacitances vary significantly depending on the applied voltage. In this paper, we propose techniques to make the capacitance of MOSFET based capacitors relatively constant over the applied voltage. We study approaches that are based on gate as well as diffusion capacitors. We study the trade-off (in terms of capacitance variation, requirement of a bias voltage and area efficiency) of all the proposed schemes. Simulation results are presented for two process technologies. We show that by using our techniques the capacitance variation across applied voltage can be reduced from 75% down to 3% for a 70nm process technology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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