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Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 16th ACM Great Lakes symposium on VLSI table of contents
Philadelphia, PA, USA
SESSION: Circuit design and modeling table of contents
Pages: 187 - 191  
Year of Publication: 2006
ISBN:1-59593-347-6
Authors
Tamer Ragheb  Rice University, Houston, Texas
Arthur Nieuwoudt  Rice University, Houston, Texas
Yehia Massoud  Rice University, Houston, Texas
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 33,   Citation Count: 4
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ABSTRACT

In this paper, we present an analytical model for fully integrated CMOS narrow-band low noise amplifiers (LNA) that enables rapid design space exploration during the synthesis process. The analytical model captures the impact of parasitics on passive components and devices to accurately predict both impedance matching and noise figure. Our results indicate that the model provides on average 39.8% better accuracy in noise figure than several current analytical modeling techniques with five orders of magnitude improvement in simulation time when compared with a circuit-level simulator. Given its speed and accuracy, our LNA model is well-suited for design space exploration.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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B. D. Smedt and G. Gielen. WATSON: Design Space Boundary Exploration and Model Generation for Analog and RFIC Design. IEEE Transactions on CAD, Feb. 2003.
 
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J.-S. Goo, et. al. A Noise Optimization Technique of Integrated Low-Noise Amplifiers. IEEE JSSC, Aug. 2002.
 
6
J. Chen and B. Shi. Impact of Intrinsic Channel Resistance on Noise Performance of CMOS LNA. IEEE Electron Device Letters, Jan. 2002.
 
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T.-K. Nguyen, et. al. CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE JSSC, Aug. 2002.
 
8
V. Govind, at. al. Design of Integrated Low Noise Amplifiers (LNA) Using Embedded Passives in Organic Substrates. IEEE Transactions on Advanced Packaging, Feb. 2004.
 
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H.-W. Chiu, S.-S. Lu, and Y.-S. Lin. A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA with 10-mW DC Power Consumption. IEEE Transactions on MTT, Mar. 2005.
 
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H.-Y. Tsui and J. Lau. SPICE Simulation and Tradeoffs of CMOS LNA Performance with Source-Degeneration Inductor. IEEE Transactions on CAS - II, Jan. 2000.
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Collaborative Colleagues:
Tamer Ragheb: colleagues
Arthur Nieuwoudt: colleagues
Yehia Massoud: colleagues