2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

ABSTRACT

This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a "Statistical Random Sampling Technique" to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data symbols at the sender side. The edges of the strobe are set within the eye of data symbols to have maximum timing margin, which makes the design inherently tolerant of jitter. Power consumption of the proposed SerDes design is 30 mW per serial link targeted to IBM Cu-11(130 nm) Technology, nearly a 2.5x improvement over the conventional design with a 60% less area requirement.

REFERENCES

• 1: R. Bhatti, et al, "Duty cycle measurement and correction using a random sampling technique", IEEE International Midwest Symposium on Circuits and Systems 2005.
• 2: R. Bhatti, et al, "Phase Measurement and Adjustment of Digital Signals Using Random Sampling Technique", IEEE International Symposium on Circuits and Systems 2006.
• 3: Jeff Draper , Jacqueline Chame , Mary Hall , Craig Steele , Tim Barrett , Jeff LaCoss , John Granacki , Jaewook Shin , Chun Chen , Chang Woo Kang , Ihn Kim , Gokhan Daglikoca, The architecture of the DIVA processing-in-memory chip, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA [doi>10.1145/514191.514197]
• 4: Cameron Dryden, Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS, Proceedings of the 23rd IEEE VLSI Test Symposium (VTS'05), p.285-291, May 01-05, 2005 [doi>10.1109/VTS.2005.79]
• 5: T. Geurts et al, "A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 /spl mu/m CMOS", Proceeding of the 30th European Solid-State Circuits Conference 2004. Page(s):487--490.
• 6: K. Iniewski , R. Badalone , M. Lapointe , M. Syrzycki, SERDES Technology for Gigabit I/O Communications in Storage Area Networking, Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop on (IWSOC'04), p.247-252, July 19-21, 2004 [doi>10.1109/IWSOC.2004.58]
• 7: S. Maggioni , A. Veggetti , A. Bogliolo , L. Croce, Random Sampling for On-Chip Characterization of Standard-Cell Propagation Delay, Proceedings of the 4th International Symposium on Quality Electronic Design, p.41, March 24-26, 2003
• 8: E. Matoglu et al, "Design and verification of multi-gigabit transmission channels using equalization techniques", Proceedings of Electronic Components and Technology 2005.
• 9: H. Partovi et al, "A 62.5 Gb/s multi-standard SerDes IC", Proceedings of Custom Integrated Circuits Conference 2003.
• 10: M. Sorna et al, "A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization", IEEE International Solid-State Circuits Conference, 2005.
• 11: E. Suckow, "Basics of High-Performance SerDes Design", http://www.analogzone.com
• 12: Stephen Sunter , Aubin Roy , J-F Cote, An Automated, Complete, Structural Test Solution for SERDES, Proceedings of the International Test Conference on International Test Conference, p.95-104, October 26-28, 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

General Terms:
Design, Measurement, Theory

Keywords:
CDR, CML driver, DLL, LVDS, PLL, SerDes, duty cycle correction (DCC), jitter and skew compensation, phase detection, standard cell based serializer and deserializer circuits for high speed signaling