SACI: statistical static timing analysis of coupled interconnects

ABSTRACT

Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a significant impact on both device (front-end of the line) and interconnect (back-end of the line) performance. Statistical static timing analysis techniques are being developed to tackle this important problem. Existing timing analysis tools divide the analysis into interconnect (wire) timing analysis and gate timing analysis. In this paper, we focus on statistical static timing analysis of coupled interconnects where crosstalk noise analysis is unavoidable. We propose a new framework for handling the effect of Gaussian and Non-Gaussian process variations on coupled interconnects. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as the line width, metal thickness, and dielectric thickness in the presence of crosstalk noise. To achieve this goal, we express the electrical parameters of the coupled interconnects in a first order (linear) form as function of changes in physical parameters and subsequently use these forms to perform accurate timing and noise analysis to produce the propagation delay and slew in the first-order forms. This work can be easily extended to consider the effect of higher order terms of the sources of variation. Experimental results show that the proposed method is capable of accurately predicting delay variation in a coupled interconnect line.

REFERENCES

• 1: R. Nassif, "Modeling and Analysis of Manufacturing Variations," CICC, pp. 223--228, 2001.
• 2: Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996675]
• 3: Soroush Abbaspour , Hanif Fatemi , Massoud Pedram, VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA [doi>10.1145/1057661.1057762]
• 4: Names and title omitted for being anonymous. To appear in Proc. of Design Automation and Test in Europe (DATE'06) , Mar. 2006.
• 5: Aseem Agarwal , Florentin Dartu , David Blaauw, Statistical gate delay model considering multiple input switching, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996746]
• 6: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 7: D. Sylvester, O.S. Nakagawa, and C. Hu. Modeling the Impact of Back End Process Variation on Circuit Performance. VLSI Technologies, Systems and Applications, Int. Symposium on, pages 58--61, 1999.
• 8: Maurizio Martina , Guido Masera, A statistical model for estimating the effect of process variations on crosstalk noise, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France [doi>10.1145/966747.966769]
• 9: T. Chern, A. Hajjar, "Statistical Timing Analysis of Coupled Interconnect Using Quadratic Delay-Change Characteristics" Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions Volume 23, Issue 12, Dec. 2004 Page(s):1677--1683.
• 10: A. Kahng, S. Muddu, D. Vidhani, "Noise and Delay Uncertainty Studies for Coupled RC Interconnects" ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International 15-18 Sept.
• 11: Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337365]
• 12: http://www.mathworld.com
• 13: Peng Li , Frank Liu , Xin Li , Lawrence T. Pileggi , Sani R. Nassif, Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction, Proceedings of the conference on Design, Automation and Test in Europe, p.958-963, March 07-11, 2005 [doi>10.1109/DATE.2005.213]
• 14: L. Daniel, O. Siong, L. Chay, K. Lee and J. White, "A multi-parameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models," IEEE Trans. CAD, vol. 23, no. 5, pp 678--693, May , 2004.
• 15: Xin Li , Jiayong Le , P. Gopalakrishnan , L. T. Pileggi, Asymptotic probability extraction for non-normal distributions of circuit performance, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.2-9, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382533]
• 16: Hongliang Chang , Vladimir Zolotov , Sambasivan Narayan , Chandu Visweswariah, Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065604]
• 17: J. Chern, J. Huang, L. Arledge, P. Li, and P. Yang, "Multilevel Metal Capacitance Models for CAD Design Synthesis Systems," IEEE Electron Devices Letters, pp. 32--34, Jan. 1992.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Measurement, Performance

Keywords:
coupled interconnect, crosstalk noise, sources of variation, statistical timing analysis