Cited By
View all- Yelamarthi KChen C(2010)Dynamic CMOS load balancing and path oriented in time optimization algorithms to minimize delay uncertainties from process variationsVLSI Design10.1155/2010/2307832010(1-13)Online publication date: 1-Jan-2010
- Yelamarthi KChen C(2009)Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS LogicIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2008.201166522:1(31-39)Online publication date: Feb-2009
- Yelamarthi KChen C(2007)Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing OptimizationProceedings of the 8th International Symposium on Quality Electronic Design10.1109/ISQED.2007.162(426-431)Online publication date: 26-Mar-2007
- Show More Cited By