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Energy-delay minimization in nanoscale domino logic

Published: 30 April 2006 Publication History

Abstract

Energy-delay product (EDP) minimization in nanoscale domino logic circuits by supply voltage selection and device sizing is presented. It is shown that the dependence of leakage current on transistor width introduces an additional factor in sizing for leakage dominant circuit blocks. A model is presented for EDP-optimal sizing of the evaluation tree of domino AND-type gates, and the effects of sizing the static output inverter and keeper on EDP are discussed. The model is applied to an 8x8 carry-save multiplier, which achieves 10% reduction in EDP at low frequencies compared to minimum width sizing.

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Cited By

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  • (2010)Dynamic CMOS load balancing and path oriented in time optimization algorithms to minimize delay uncertainties from process variationsVLSI Design10.1155/2010/2307832010(1-13)Online publication date: 1-Jan-2010
  • (2009)Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS LogicIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2008.201166522:1(31-39)Online publication date: Feb-2009
  • (2007)Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing OptimizationProceedings of the 8th International Symposium on Quality Electronic Design10.1109/ISQED.2007.162(426-431)Online publication date: 26-Mar-2007
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    cover image ACM Conferences
    GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI
    April 2006
    450 pages
    ISBN:1595933476
    DOI:10.1145/1127908
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 30 April 2006

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    Author Tags

    1. delay
    2. domino
    3. energy
    4. leakage
    5. low voltage

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    View all
    • (2010)Dynamic CMOS load balancing and path oriented in time optimization algorithms to minimize delay uncertainties from process variationsVLSI Design10.1155/2010/2307832010(1-13)Online publication date: 1-Jan-2010
    • (2009)Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS LogicIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2008.201166522:1(31-39)Online publication date: Feb-2009
    • (2007)Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing OptimizationProceedings of the 8th International Symposium on Quality Electronic Design10.1109/ISQED.2007.162(426-431)Online publication date: 26-Mar-2007
    • (2006)Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing2006 13th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2006.379631(1101-1104)Online publication date: Dec-2006

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