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A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models

Published: 30 April 2006 Publication History

Abstract

This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.

References

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  • (2018)Related WorkPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_2(17-48)Online publication date: 15-Dec-2018
  • (2013)A modular and generic router TLM model for speedup network-on-chip topology generation10th International Multi-Conferences on Systems, Signals & Devices 2013 (SSD13)10.1109/SSD.2013.6564035(1-7)Online publication date: Mar-2013
  • (2013)Scalable parallel simulation of networks on chip2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NoCS.2013.6558402(1-8)Online publication date: Apr-2013
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cover image ACM Conferences
GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI
April 2006
450 pages
ISBN:1595933476
DOI:10.1145/1127908
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 April 2006

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Author Tags

  1. SystemC
  2. energy model
  3. network-on-chip

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GLSVLSI06
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GLSVLSI06: Great Lakes Symposium on VLSI 2006
April 30 - May 1, 2006
PA, Philadelphia, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2018)Related WorkPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_2(17-48)Online publication date: 15-Dec-2018
  • (2013)A modular and generic router TLM model for speedup network-on-chip topology generation10th International Multi-Conferences on Systems, Signals & Devices 2013 (SSD13)10.1109/SSD.2013.6564035(1-7)Online publication date: Mar-2013
  • (2013)Scalable parallel simulation of networks on chip2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NoCS.2013.6558402(1-8)Online publication date: Apr-2013
  • (2011)Design and performance evaluation of on chip network with Transaction Level ModelingICM 2011 Proceeding10.1109/ICM.2011.6177373(1-6)Online publication date: Dec-2011
  • (2009)An energy and performance exploration of network-on-chip architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201123217:3(319-329)Online publication date: 1-Mar-2009
  • (2009)A high level power model for Network-on-Chip (NoC) routerComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02335:6(837-845)Online publication date: 1-Nov-2009
  • (2008)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis FrameworkProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397991(107-116)Online publication date: 7-Apr-2008
  • (2008)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis FrameworkSecond ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)10.1109/NOCS.2008.4492730(107-116)Online publication date: Apr-2008
  • (2007)A Power and Energy Exploration of Network-on-Chip ArchitecturesProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.6(163-172)Online publication date: 7-May-2007
  • (2007)Control and datapath decoupling in the design of a NoC switch: area, power and performance implications2007 International Symposium on System-on-Chip10.1109/ISSOC.2007.4427438(1-4)Online publication date: Nov-2007

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