A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models

ABSTRACT

This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.This paper presents a system-level Network-on-Chip simulation platform integrating the transaction-level performance model of NoC components and their architecture-level energy models. The transaction-level model written in SystemC enables fast simulation speed and the architectural energy model estimates communication energy, including both dynamic and leakage, dissipating on routers and links through the transaction-level simulation. This power model supports temporal power profiling for each NoC component and spatial power snapshots for the whole NoC, making it easy to inspect the power implications under application workloads. Applying this energy model on 8 deep sub-micron CMOS processes from 180nm to 45nm, we reveal an average 2.8X leakage power increase for each technology evolution. With temporal and spatial profiling for burst-mode applications, the power hungry portions in both time- and space-domains can be identified, and in turn it provides useful information for the energy-aware NoC design space exploration for the future nanoscale IC technologies.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.4 Performance Analysis and Design Aids**
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
      B.7.2 Design Aids

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design

General Terms:
Design, Experimentation, Performance, Verification

Keywords:
SystemC, energy model, network-on-chip