| REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs |
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Conference On Computing Frontiers
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Proceedings of the 3rd conference on Computing frontiers
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Ischia, Italy
SESSION: Reconfigurable and autonomic computing
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Pages: 403 - 412
Year of Publication: 2006
ISBN:1-59593-302-6
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Authors
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Heiko Kalte
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University of Western Australia, Crawley, WA
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Mario Porrmann
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Heinz Nixdorf Institute System and University of Paderborn, Paderborn, Germany
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Downloads (6 Weeks): 4, Downloads (12 Months): 90, Citation Count: 0
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ABSTRACT
One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can only be determined during runtime according to the current resource allocation. This requires relocating each task from its original position after place and route to an area of available resources. The process of relocating tasks can result in a major time overhead. In order to solve this problem we have developed the REPLICA2Pro (Relocation per online Configuration Alteration in Virtex-2/-Pro) filter, which is capable of performing task relocations by manipulating the task's bitstream during the regular allocation process without any extra time overhead. The filter architecture, our reconfigurable system approach as well as our design flow and an experimental system setup are presented in this paper.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H. Kalte, M. Porrmann, and U. Ruckert. System-on-programmable-chip approach enabling online fine-grained 1D-placement. In Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), Santa Fé, New Mexico, 2004.
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M. Ullmann, M. Hübner, B. Grimm, and J. Becker. An fpga run-time system for dynamical on-demand reconfiguration. In Proc. of the 18th International Parallel and Distributed Processing Symposium, 2004.
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Christophe Bobda , Mateusz Majer , Ali Ahmadinia , Thomas Haller , Andre Linarth , Jurgen Teich , Jan van der Veen, The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform, Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), p.319-320, April 18-20, 2005
[doi> 10.1109/FCCM.2005.63]
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H. Kalte, G. Lee, M. Porrmann, U. Rückert: Study on Column Wise Design Compaction for Reconfigurable Systems. In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), Brisbane, Australia, December 6-8, 2004.
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E. Horta, J. W. Lockwood. PARBIT: A tool to transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs). Tech. Rep. WUCS-01-13, Washington University, July 2001.
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H. Kalte, G. Lee, M. Porrmann, U. Ruckert: REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. In Proc. of the 12th Reconfigurable Architectures Workshop (RAW), Denver, Colorado, USA, April 2005.
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Xilinx Inc.: Xilinx Virtex-II Pro and Xilinx Virtex-II Pro X FPGA user guide, 2005. URL: http://www.xilinx.xom
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Xilinx Application Notes 290: Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, 2002, http://www.xilinx.com.
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H. Kalte, M. Porrmann and U. Rückert: A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
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M. Köster, H. Kalte, M. Porrmann: Task Placement for Heterogeneous Reconfigurable Architectures. In: Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), Singapore, December 11-14, 2005. (Accepted for publication)
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OpenCores: http://www.OpenCores.org
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