Evaluation of the field-programmable cache: performance and energy consumption

ABSTRACT

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based on field-programmable technology that is intended to deliver high performance at low energy consumption. In this paper, we evaluate the performance and energy consumption of a run-time algorithm when used to manage a field-programmable L1 data cache. The adaptation strategy is based on two techniques: a learning process provides the best cache configuration for each program phase, and a recognition process detects program phase changes by using data working-set signatures to activate a low-overhead reconfiguration mechanism. Our proposals achieve performance improvement and cache energy saving at the same time. Considering a design scenario driven by performance constraints, we show that processor execution time and cache energy consumption can be reduced on average by 15.2% and 9.9% compared to a non-adaptive high-performance microarchitecture. Alternatively, when energy saving is prioritized and considering a non-adaptive energy-efficient microarchitecture as baseline, cache energy and processor execution time are reduced on average by 46.7% and 9.4% respectively. In addition to comparing to conventional microarchitectures, we show that the proposed microarchitecture achieves better performance and more cache energy reduction than other configurable caches.

REFERENCES

• 1: R. Iris Bahar , Gianluca Albera , Srilatha Manne, Power and performance tradeoffs using various caching strategies, Proceedings of the 1998 international symposium on Low power electronics and design, p.64-69, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.295115]
• 2: R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. A dynamically tunable memory hierarchy. IEEE Tran. Computers 52(10):1243--1257, 2003.
• 3: D. Benitez, J. Moure, D. Rexachs, and E. Luque. Performance and power evaluation of an intelligently adaptive data cache. Lecture Notes in Computer Science 3769: 363--375, December 2005.
• 4: D. Boggs, A. Baktha, J. Hawkins, D. Marr, J. Miller, P. Roussel, R. Singhal, B. Toll, and K. Venkatraman. The microarchitecture of the intel pentium 4 processor on 90nm technology. Intel Technology Journal http://developer.intel.com/technology/itj,February 2004.
• 5: D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308, University of Wisconsin-Madison. Computer Sciencies Department, 1996.
• 6: Ashutosh S. Dhodapkar , James E. Smith, Managing multi-configuration hardware via dynamic working set analysis, Proceedings of the 29th annual international symposium on Computer architecture, p.233, May 25-29, 2002, Anchorage, Alaska
• 7: Ashutosh S. Dhodapkar , James E. Smith, Comparing Program Phase Detection Techniques, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.217, December 03-05, 2003
• 8: Richard O. Duda , Peter E. Hart , David G. Stork, Pattern Classification (2nd Edition), Wiley-Interscience, 2000
• 9: Marc Epalza , Paolo Ienne , Daniel Mlynek, Adding Limited Reconfigurability to Superscalar Processors, Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, p.53-62, September 29-October 03, 2004 [doi>10.1109/PACT.2004.5]
• 10: Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi, Timekeeping in the memory system: predicting and optimizing memory behavior, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
• 11: Michael C. Huang , Jose Renau , Josep Torrellas, Positional adaptation of processors: application to energy reduction, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 12: Intel. Intel XScale Microarchitecture for the PXA255 Processor. User Manual Intel, 2003.
• 13: Changkyu Kim , Doug Burger , Stephen W. Keckler, An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 14: Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 15: C. Lee , D. A. Landgrebe, Feature Extraction Based on Decision Boundaries, IEEE Transactions on Pattern Analysis and Machine Intelligence, v.15 n.4, p.388-400, April 1993 [doi>10.1109/34.206958 ]
• 16: Grigorios Magklis , Michael L. Scott , Greg Semeraro , David H. Albonesi , Steven Dropsho, Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 17: P. Shivakumar and N. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Technical Report 2001/2, Compact WRL, 2001.
• 18: Parthasarathy Ranganathan , Sarita Adve , Norman P. Jouppi, Reconfigurable caches and their application to media processing, Proceedings of the 27th annual international symposium on Computer architecture, p.214-224, June 2000, Vancouver, British Columbia, Canada
• 19: Greg Semeraro , Grigorios Magklis , Rajeev Balasubramonian , David H. Albonesi , Sandhya Dwarkadas , Michael L. Scott, Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.29, February 02-06, 2002
• 20: Timothy Sherwood , Erez Perelman , Greg Hamerly , Brad Calder, Automatically characterizing large scale program behavior, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 21: Timothy Sherwood , Suleyman Sair , Brad Calder, Phase tracking and prediction, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 22: Stamatis Vassiliadis , Stephan Wong , Sorin Cotofana, The MOLEN rho-mu-Coded Processor, Proceedings of the 11th International Conference on Field-Programmable Logic and Applications, p.275-285, August 27-29, 2001
• 23: Se-Hyun Yang , Babak Falsafi , Michael D. Powell , T. N. Vijaykumar, Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.151, February 02-06, 2002
• 24: Zhi Alex Ye , Andreas Moshovos , Scott Hauck , Prithviraj Banerjee, CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit, Proceedings of the 27th annual international symposium on Computer architecture, p.225-235, June 2000, Vancouver, British Columbia, Canada
• 25: Chuanjun Zhang , Frank Vahid , Walid Najjar, A highly configurable cache architecture for embedded systems, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design, Performance

Keywords:
adaptive processors, performance evaluation, reconfigurable cache memory, run-time adaptation, static and dynamic energy consumption