Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs

ABSTRACT

A Debug Port Controller (DPC) architecture, designed for re-use in multiple System-on-Chip (SoC) Integrated Circuits (ICs) is presented. The DPC incorporates security protection against unauthorized access along with advanced debugging features such as long chain debugging, universal BIST engines control, and generic serial interfaces. An implemented security architecture of DPC is presented together with an overall IC security scheme. DPC is the most important part of this IC security scheme. The suggested architecture demonstrates extensive use of the debug process, and re-use of the DPC in multiple SoC ICs without the need of adopting its design for a specific SoC. The implementation of the DPC for IEEE1149.1 standard is presented and the hardware realization of the proposed architecture is described in detail. The DPC that incorporates the proposed architecture has been designed in a 90 nm CMOS process as an integral part of several SoC ICs.

REFERENCES

• 1: T. Rahal-Arabi, G. Taylor, A JTAG Based AC Leakage Self Test, VLSI Circuits Digest of Technical Papers Symp., 2001, pp. 205--206
• 2: Standard Test Access Port and Boundary-Scan Architecture, IEEE standard 1149.1-2001, 2001
• 3: D. Y. Jung, S. H. Kwak, M. K. Lee, Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture, Proc. 2002 IEEE Asia-Pacific Conference on ASIC, pp.209 -- 212, Aug. 2002
• 4: Ingeol Chun; Chaedeok Lim, ES-debugger: the flexible embedded system debugger based on JTAG technology, Intl. Conf. on Advanced Communication Technology (ICACT 2005), Volume 2, pp. 900 -- 903, Feb. 2005
• 5: Y. Amon, D. Akselrod, E. Segev, Integrated Circuit and a Method for Testing a Multi-Tap Integrated Circuit, an International patent application, PCT/EP2004/014805, filed on Nov. 22, 2004
• 6: Alfred L. Crouch, Design for Test: For Digital Integrated Circuits, Prentice Hall PTR, Upper Saddle River, NJ, 1999
• 7: Bo Yang , Kaijie Wu , Ramesh Karri, Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard, Proceedings of the International Test Conference on International Test Conference, p.339-344, October 26-28, 2004
• 8: W. Moyer and M. Fitzimmons, Integrated Circuit Security and Method therefore, Patent application No. 10/100,462, Pub. # US 2003/0177373 A1, Publ. Date Sep. 18, 2003, Motorola Inc
• 9: D. Akselrod, Y. Amon, A. Ashkenazi, Integrated Circuit and a Method for Secure Testing, an International patent application, PCT/EP2004/014804, filed on Nov. 22, 2004
• 10: A. Ashkenazi, Securing Smartphones from the Inside Out, Design Seminars 2005 Proceedings, Embedded Systems Conference San Francisco 2005, 3G Cellular Design Seminar, session 3GC-702.