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Energy-efficient FPGA interconnect design

Published: 06 March 2006 Publication History

Abstract

Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is demonstrated that the delay of a full-swing, fully-buffered interconnect architecture can be matched by a low-swing solution that dissipates significantly less power and contains a mix of buffer and pass-gate switches. The actual energy savings depend on the specifics of the interconnect design and applications involved. For the considered fine-grain FPGA example, energy savings are observed to range from a factor 4.7 for low-load critical nets to a factor 2.8 for high-load critical nets. The results are obtained from circuit simulations in a 0.13 μm CMOS technology for various benchmarks.

References

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E. Kusse, J. Rabaey, Low-Energy Embedded FPGA Structures, International Symposium of Low Power Electronic Design (ISLPED), Monterey, CA, USA, 1998
[2]
L. Shang, A. Kaviani, K. Bathala, Dynamic Power Consumption in Virtex-II FPGA Family, FPGA, February 2000, pp. 157--164
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J. H. Anderson et. al., Active Leakage Power Optimization for FPGAs, ACM International Symposium on FPGAs, Monterey, CA, 22-24 February 2004
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A. Rahman, V. Polavarapuv, Evaluation of Low-Leakage Design Techniques for FPGAs, ACM International Symposium on FPGAs, Monterey, CA, 22-24 February 2004
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F. Li et. al., Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics, ACM International Symposium on FPGAs, Monterey, CA, 22-24 February 2004
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V. George, H. Zhang, J. Rabeay, The Design of a Low Energy FPGA, International Symposium of Low Power Electronic Design (ISLPED), San Diego, CA, USA, 1999, pp. 188--193
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V. Betz, J. Rose, A. Marquardt, Architecture and CAD for deep-submicron FPGAs, Kluwer Academic Publishers, 1999.
[8]
H. Zhang et. al., Low-Swing On-Chip Signalling Techniques: Effectiveness and Robustness, IEEE Transactions On VLSI, Vol. 8, No. 3, June 2000, pp.264--272

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Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Designers' forum
March 2006
262 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 45 of 45 submissions, 100%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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