A mixed-signal verification kit for verification of analogue-digital circuits

ABSTRACT

This paper presents an innovative approach for analogue and mixed-signal verification. It consists in a "verification kit" that makes use of concepts used in state-of-art digital verification, such as automatic results collection, coverage elaboration, data checking capability, pseudo-random and constrained stimuli generation. Using a Bandgap cell as case study, the paper shows as the presented approach allows a precise definition of the verification space and a saving of more than 50% of the total verification effort respect traditional verification methodologies. The paper shows also how the approach can be extended to more complex mixed-signal systems.

REFERENCES

• 1: C. Brown, "Mastering of Mixed-Signal Verification" EETIMES, 17 March, 2004
• 2: Bill Luo, Jim Lear, "A Unified Functional Verification Approach for Mixed Analog-Digital ASIC Designs", Legerty INC, DesignCon 2003
• 3: Koji Ara , Kei Suzuki, A Proposal for Transaction-Level Verification with Component Wrapper Language, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20082, March 03-07, 2003
• 4: "IEEE Std VHDL 1076.1-99: The Analog and Mixed Signal Extension for VHDL", 1999
• 5: B. Li, L. Jia, H. Tenhunen, "Optimization of analog modelling and Simulation", Proc. of the 5th International Conference on Solid-State and Integrated Circuit Technology, 1999, Beijing, China, pp. 385--388
• 6: A. Ginés , E. Peralías , A. Rueda , R. Seepold , N. Madrid, A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects, Proceedings of the conference on Design, automation and test in Europe, p.310, March 04-08, 2002
• 7: Eduardo Peralías , Antonio J. Acosta , Adoración Rueda , José L. Huertas, A VHDL-based methodology for the design and verification of pipeline A/D converters, Proceedings of the conference on Design, automation and test in Europe, p.534-538, March 27-30, 2000, Paris, France [doi>10.1145/343647.343842]
• 8: R. Mariani, M. Chiavacci, G. Bonfini "Foundamentals of a novel approach for mixed analogue-digital verification", 9th IEEE European Test Symposium, Informal Session, Ajaccio (Corsica), 23--26 May 2004
• 9: G. Bonfini, M. Chiavacci, R. Mariani, R. Saletti "A New Verification Approach for Mixed-Signal Systems", 2005 IEEE International Behavioral Modeling and Simulation Conference(BMAS 2005), 22-23 September 2005, San Jose, California, USA, accepted for web publication
• 10: G. Bonfini, M. Chiavacci, F. Colucci, F. Gronchi, R. Mariani, E. Pescari, A. Sterpin "Fault Coverage in a New Mixed-Signal Verification Environment", In Proc. of 11th International Mixed-Signal Testing Workshop (IMSTW), 27--29 June 2005, Cannes, Franc, pp.148--154
• 11: R. J. Widlar, "New developments in IC voltage regulators", IEEE J. Solid-State Circuits, vol. SC-6, pp. 2--7, Feb. 1971
• 12: A. P. Brokaw, "A simple three-terminal IC bandgap reference", IEEE J. Solid-State Circuits, vol. SC-9, pp. 388--393, Dec. 1974
• 13: Cadence's Specman tool, www.cadence.com
• 14: IEEE 1647: http://www.ieee1647.org/index.html
• 15: Verilog-AMS Language Reference Manual: "Analog & Mixed-Signal Exstension to Verilog HDL", version 2.1, January 20, 2003