ACM Home Page
Please provide us with feedback. Feedback
Software-friendly HW/SW co-simulation: an industrial case study
Full text PdfPdf (139 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Designers' forum table of contents
Munich, Germany
SESSION: Specification and verification table of contents
Pages: 100 - 105  
Year of Publication: 2006
ISBN ~ ISSN:478061 , 3-9810801-0-6
Authors
Juanjo Noguera  Large-Format Technology Lab, Hewlett-Packard, Sant Cugat del Valles, Barcelona (Spain)
Luis Baldez  Large-Format Technology Lab, Hewlett-Packard, Sant Cugat del Valles, Barcelona (Spain)
Narcis Simon  Large-Format Technology Lab, Hewlett-Packard, Sant Cugat del Valles, Barcelona (Spain)
Lluis Abello  Large-Format Technology Lab, Hewlett-Packard, Sant Cugat del Valles, Barcelona (Spain)
Sponsors
EDAA : European Design and Automation Association
: The EDA Consortium
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 29,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   

ABSTRACT

This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test their software with their own tools and environment using an accurate simulated ASIC (Application Specific Integrated Circuit) model.The solution presented here enables a smooth and early ASIC and SW integration, which reduces the project development time and improves the ASIC design quality (i.e., SW engineers can help in the ASIC verification and ASIC engineers can help in the SW development). In this solution, the real and full software (i.e., multi-threaded application) runs in its native environment with minimal changes and interfaces with a simulated ASIC model using sockets. We have tested this approach on a pilot-project, which has demonstrated the feasibility of this co-development methodology.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
 
4
CODES+ISSS'03 Panel on System Level Design Tools, http://www.ece.uci.edu/codes+isss/
 
5
Mojy Chian, "Economics of SOC Development: How can we make this a profitable endeavor?"; Invited talk at CODES+ISSS'03
6
7
 
8
 
9
10
Collaborative Colleagues:
Juanjo Noguera: colleagues
Luis Baldez: colleagues
Narcis Simon: colleagues
Lluis Abello: colleagues