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GALS networks on chip: a new solution for asynchronous delay-insensitive links

Published: 06 March 2006 Publication History

Abstract

In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same.

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Cited By

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  • (2016)CrossOverProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972086(1183-1188)Online publication date: 14-Mar-2016
  • (2010)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871091(679-684)Online publication date: 8-Mar-2010
  • (2010)Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOsProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787335(267-276)Online publication date: 17-May-2010
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Information

Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Designers' forum
March 2006
262 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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  • Article

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DATE '06 Paper Acceptance Rate 45 of 45 submissions, 100%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2016)CrossOverProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972086(1183-1188)Online publication date: 14-Mar-2016
  • (2010)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871091(679-684)Online publication date: 8-Mar-2010
  • (2010)Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOsProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787335(267-276)Online publication date: 17-May-2010
  • (2010)A new physical routing approach for robust bundled signaling on NoC linksProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785485(3-8)Online publication date: 16-May-2010
  • (2010)A low-area multi-link interconnect architecture for GALS chip multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201791218:5(750-762)Online publication date: 1-May-2010
  • (2007)Relieving physical issues in new NoC-based SoCsProceedings of the 2nd international conference on Nano-Networks10.5555/1459290.1459304(1-5)Online publication date: 24-Sep-2007
  • (2007)Voltage-frequency island partitioning for GALS-based networks-on-chipProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278509(110-115)Online publication date: 4-Jun-2007

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