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Automatic identification of application-specific functional units with architecturally visible storage

Published: 06 March 2006 Publication History

Abstract

Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8x over pure software execution. Moreover, the number of required memory-access instructions is reduced by two thirds on average, suggesting corresponding benefits on energy consumption.

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Cited By

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  • (2018)Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276912526:3(445-456)Online publication date: 1-Mar-2018
  • (2018)StitchProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00054(575-587)Online publication date: 2-Jun-2018
  • (2014)Automatic custom instruction identification in memory streaming algorithmsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656114(1-9)Online publication date: 12-Oct-2014
  • Show More Cited By

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Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2018)Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276912526:3(445-456)Online publication date: 1-Mar-2018
  • (2018)StitchProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00054(575-587)Online publication date: 2-Jun-2018
  • (2014)Automatic custom instruction identification in memory streaming algorithmsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656114(1-9)Online publication date: 12-Oct-2014
  • (2011)Accelerating loops for coarse grained reconfigurable architectures using instruction extensionsProceedings of the 2011 ACM Symposium on Research in Applied Computation10.1145/2103380.2103445(314-318)Online publication date: 2-Nov-2011
  • (2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
  • (2009)Heterogeneous coarse-grained processing elementsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874752(542-547)Online publication date: 20-Apr-2009
  • (2008)Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extensionProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393987(241-246)Online publication date: 11-Aug-2008
  • (2008)Recurrence-aware instruction set selection for extensible embedded processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200186316:10(1259-1267)Online publication date: 1-Oct-2008
  • (2007)Increasing data-bandwidth to instruction-set extensions through register clusteringProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326108(166-171)Online publication date: 5-Nov-2007
  • (2006)Code transformation strategies for extensible embedded processorsProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176791(242-252)Online publication date: 22-Oct-2006

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