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A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Power grid and large interconnect network analysis table of contents
Pages: 39 - 44  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Baohua Wang  University of Michigan, Ann Arbor
Pinaki Mazumder  University of Michigan, Ann Arbor
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

This paper derives the multi-layer heat conduction Green's function, by integrating the eigen-expansion technique and the classic transmission line theories, and presents a logarithmic full-chip thermal analysis algorithm, which is verified by comparisons with a computational fluid dynamics tool (FLUENT). The paper considers Dirichlet's and general heat convection boundary conditions at chip surfaces. Experimental results show that the algorithm offers superior computing speed, compared to FLUENT and traditional Green's function based methods. The paper also studies the limitations of the traditional single-layer thermal model.


REFERENCES

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Collaborative Colleagues:
Baohua Wang: colleagues
Pinaki Mazumder: colleagues