A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes

ABSTRACT

An on-chip interconnect is implemented with 3Gbps/wire bandwidth performance with 8:1 serialization scheme. Such high-speed serialization is achieved using a novel serialization scheme, Wave-Front-Train. In order to apply such high-speed link technique to Network-on-Chip channels, three adaptive control schemes are used: supply voltage dependent reference voltage control, phase compensation scheme with self-calibrating function, and adaptive bandwidth control. The chip is fabricated using 0.18μm CMOS technology.

REFERENCES

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