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Test generation for combinational quantum cellular automata (QCA) circuits
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: Design methodologies for emerging technologies table of contents
Pages: 311 - 316  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Pallav Gupta  Princeton University, Princeton, NJ
Niraj K. Jha  Princeton University, Princeton, NJ
Loganathan Lingappan  Princeton University, Princeton, NJ
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent attention and shows immense promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC benchmarks that use majority gates as primitives.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
"International Technology Roadmap for Semiconductors." http://public.itrs.net
 
2
P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," J. Applied Physics, vol. 75, no. 3, pp. 1818--1825, Feb. 1994.
 
3
I. Amlani, A. O. Orlov, G. L. Snider, and C. S. Lent, "Demonstration of a six-dot quantum cellular automata system," Appl. Phys. Lett., vol. 72, no. 17, pp. 2179--2181, Apr. 1998.
 
4
I. Amlani, A. O. Orlov, G. Toth, C. S. Lent, G. Bernstein, and G. L. Snider, "Digital logic gate using quantum-dot cellular automata," Science, vol. 284, no. 5412, pp. 289--291, Apr. 1999.
 
5
M. Lieberman, S. Chellamma, B. Varughese, Y. Wang, C. S. Lent, G. Bernstein, G. L. Snider, and F. Peiris, "Quantum-dot cellular automata at a molecular scale," Ann. New York Acad. Sci., vol. 960, pp. 225--239, 2002.
 
6
K. Hennessy and C. S. Lent, "Clocking of molecular quantum-dot cellular automata," J. Vac. Sci. Technol., vol. 19, no. 5, pp. 1752--1755, Sept. 2001.
 
7
M. B. Tahoori, J. Huang, M. Momenzadeh, and F. Lombardi, "Testing of quantum cellular automata," IEEE Trans. Nanotechnol., vol. 3, no. 4, pp. 432--442, Dec. 2004.
 
8
 
9
R. Zhang, K. Walus, W. Wang, and G. A. Jullien, "A method of majority logic reduction for quantum cellular automata," IEEE Trans. Nanotechnol., vol. 3, no. 4, pp. 443--450, Dec. 2004.
 
10
11
 
12
K. Walus, T. Dysart, G. A. Jullien, and R. A. Budiman, "QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 26--31, Mar. 2004.
 
13
 
14
 
15
M. Momenzadeh, M. B. Tahoori, J. Huang, and F. Lombardi, "Quantum cellular automata: New defects and faults for new devices," in Proc. Int. Parallel and Distributed Processing Symp., Apr. 2004, pp. 207--214.
 
16
K. Walus, G. Schulhof, and G. A. Jullien, "High level exploration of quantum-dot cellular automata," in Proc. Conf. Signals, Systems, and Computers, Nov. 2004, pp. 7--10.
 
17
T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. Computer-Aided Design, vol. 11, no. 1, pp. 4--15, Jan. 1992.
 
18
 
19
 
20
R. Lisanke, "Logic synthesis and optimization benchmarks," Microelectronics Center of North Carolina, Tech. Rep., 1988.
 
21

Collaborative Colleagues:
Pallav Gupta: colleagues
Niraj K. Jha: colleagues
Loganathan Lingappan: colleagues