ACM Home Page
Please provide us with feedback. Feedback
A systematic IP and bus subsystem modeling for platform-based system design
Full text PdfPdf (185 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: System level modelling table of contents
Pages: 560 - 564  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Junhyung Um  CAE Center, SoC R&D, Samsung Electronics, Korea
Woo-Cheol Kwon  CAE Center, SoC R&D, Samsung Electronics, Korea
Sungpack Hong  CAE Center, SoC R&D, Samsung Electronics, Korea
Young-Taek Kim  CAE Center, SoC R&D, Samsung Electronics, Korea
Kyu-Myung Choi  CAE Center, SoC R&D, Samsung Electronics, Korea
Jeong-Taek Kong  CAE Center, SoC R&D, Samsung Electronics, Korea
Soo-Kwan Eo  CAE Center, SoC R&D, Samsung Electronics, Korea
Taewhan Kim  Seoul National University, Seoul, Korea
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 47,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  
Save this Article to a Binder    Display Formats: BibTex  EndNote ACM Ref   

ABSTRACT

The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally accepted that the system modeling should be performed in two steps; In the first step, a fast but some inaccurate system modeling is considered to facilitate the simultaneous development of software and hardware. The second step then refines the models of the software and hardware blocks (i.e., IPs) to increase the simulation accuracy for the system performance analysis. Here, one critical factor required for a successful system modeling is a systematic modeling of the IP blocks and bus subsystem connecting the IPs. In this respect, this work addresses the problem of systematic modeling of the IPs and bus subsystem in different levels of refinements. In the experiments, we found that by applying our proposed IP and bus modeling methods to the MPEG-4 application, we are able to achieve 4x performance improvement and at the same time, reduce the software development time by 35%, compared to that by conventional modeling methods.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. Keutzer, et al., "System-level design: orthogonalization of concerns and platform-based design", IEEE TCAD, 2000.
2
3
 
4
 
5
J. Notbauer, et al., "Verification and management of a multimillion-gate embedded core design", DATE, 1999.
6
 
7
I. Moussa, et al., "Exploring SW performance using SoC transaction-level modeling", DAC, 2003.
8
 
9
 
10
 
11
12
13
14
 
15
16
 
17
 
18
 
19
 
20
AHB CLI Specification www.arm.com/armtech/ahbcli
 
21
Maxsim, AXYS Design Inc., m http://www.axysdesign.com
Collaborative Colleagues:
Junhyung Um: colleagues
Woo-Cheol Kwon: colleagues
Sungpack Hong: colleagues
Young-Taek Kim: colleagues
Kyu-Myung Choi: colleagues
Jeong-Taek Kong: colleagues
Soo-Kwan Eo: colleagues
Taewhan Kim: colleagues