| A systematic IP and bus subsystem modeling for platform-based system design |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
table of contents
Munich, Germany
SESSION: System level modelling
table of contents
Pages: 560 - 564
Year of Publication: 2006
ISBN:3-9810801-0-6
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Authors
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Junhyung Um
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Woo-Cheol Kwon
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Sungpack Hong
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Young-Taek Kim
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Kyu-Myung Choi
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Jeong-Taek Kong
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Soo-Kwan Eo
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CAE Center, SoC R&D, Samsung Electronics, Korea
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Taewhan Kim
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Seoul National University, Seoul, Korea
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European Design and Automation Association
3001 Leuven, Belgium, Belgium
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ABSTRACT
The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally accepted that the system modeling should be performed in two steps; In the first step, a fast but some inaccurate system modeling is considered to facilitate the simultaneous development of software and hardware. The second step then refines the models of the software and hardware blocks (i.e., IPs) to increase the simulation accuracy for the system performance analysis. Here, one critical factor required for a successful system modeling is a systematic modeling of the IP blocks and bus subsystem connecting the IPs. In this respect, this work addresses the problem of systematic modeling of the IPs and bus subsystem in different levels of refinements. In the experiments, we found that by applying our proposed IP and bus modeling methods to the MPEG-4 application, we are able to achieve 4x performance improvement and at the same time, reduce the software development time by 35%, compared to that by conventional modeling methods.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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K. Keutzer, et al., "System-level design: orthogonalization of concerns and platform-based design", IEEE TCAD, 2000.
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2
|
Alberto Sangiovanni-Vincentelli , Luca Carloni , Fernando De Bernardinis , Marco Sgroi, Benefits and challenges for platform-based design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996684]
|
 |
3
|
|
| |
4
|
|
| |
5
|
J. Notbauer, et al., "Verification and management of a multimillion-gate embedded core design", DATE, 1999.
|
 |
6
|
|
| |
7
|
I. Moussa, et al., "Exploring SW performance using SoC transaction-level modeling", DAC, 2003.
|
 |
8
|
|
| |
9
|
|
| |
10
|
Ney Calazans , Edson Moreno , Fabiano Hessel , Vitor Rosa , Fernando Moraes , Everton Carara, From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study, Proceedings of the 16th symposium on Integrated circuits and systems design, p.355, September 08-11, 2003
|
| |
11
|
|
 |
12
|
|
 |
13
|
Yuichi Nakamura , Kouhei Hosokawa , Ichiro Kuroda , Ko Yoshikawa , Takeshi Yoshimura, A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996655]
|
 |
14
|
Haris Lekatsas , Jörg Henkel , Srimat Chakradhar , Venkata Jakkula , Murugan Sankaradass, CoCo: a hardware/software platform for rapid prototyping of code compression technologies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.775912]
|
| |
15
|
M. Caldari , M. Conti , M. Coppola , S. Curaba , L. Pieralisi , C. Turchetti, Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20026, March 03-07, 2003
|
 |
16
|
|
| |
17
|
|
| |
18
|
Ali Sayinta , Gorkem Canverdi , Marc Pauwels , Amer Alshawa , Wim Dehaene, A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20095, March 03-07, 2003
|
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19
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Osamu Ogawa , Sylvain Bayon de Noyer , Pascal Chauvet , Katsuya Shinohara , Yoshiharu Watanabe , Hiroshi Niizuma , Takayuki Sasaki , Yuji Takai, A Practical Approach for Bus Architecture Optimization at Transaction Level, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20176, March 03-07, 2003
|
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20
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AHB CLI Specification www.arm.com/armtech/ahbcli
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21
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Maxsim, AXYS Design Inc., m http://www.axysdesign.com
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