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Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe: Proceedings table of contents
Munich, Germany
SESSION: SoC targeted mixed-signal test solutions table of contents
Pages: 652 - 657  
Year of Publication: 2006
ISBN:3-9810801-0-6
Authors
Chunsheng Liu  University of Nebraska-Lincoln, Omaha, NE
Vikram Iyengar  IBM Microelectronics, Essex Jct, VT
Sponsors
: The EDA Consortium
EDAA : European Design and Automation Association
IEEE-CS\DATC : The IEEE Computer Society
Publisher
European Design and Automation Association  3001 Leuven, Belgium, Belgium
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ABSTRACT

Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem in Network-on-Chip (NoC) systems through thermal optimization using variable-rate on-chip clocking. We control the core temperatures during test scheduling by assigning different test clock frequencies to cores. We present two heuristics to achieve thermal optimization and reduced test time. Experimental results for example NoC systems show that the proposed method can guarantee thermal safety and yield better thermal balance, compared to previous methods using power constraints. Test application time is also reduced.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Chunsheng Liu: colleagues
Vikram Iyengar: colleagues