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Efficient factorization of DSP transforms using taylor expansion diagrams

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Q. Ren,

S. AskarAuthors Info & Claims

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

Pages 754 - 755

Published: 06 March 2006 Publication History

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Abstract

This paper describes an efficient method to perform factorization of DSP transforms based on Taylor Expansion Diagram (TED). It is shown that TED can efficiently represent and manipulate mathematical expressions. We demonstrate that it enables efficient factorization of arithmetic expressions of DSP transforms, resulting in a simplification of the computation.

References

[1]

M. Ciesielski, P. Kalla, Z. Zeng, and B. Rouzeyre. Taylor Expansion Diagrams: A Compact Canonical Representation with Applications to Symbolic Verification. In Design Automation and Test in Europe, DATE-02, pages 285--289, 2002.

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[2]

M. Püschel, J. M. F. Moura, J. Johnson, D. Padua, M. Veloso, B. W. Singer, J. Xiong, F. Franchetti, A. Gačić, Y. Voronenko, K. Chen, R. W. Johnson, and N. Rizzolo. SPIRAL: Code generation for DSP transforms. Proceedings of the IEEE, special issue on "Program Generation, Optimization, and Adaptation", 93(2), 2005.

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Pérez JSánchez PFernández VDe Micheli GAl-Hashimi BMueller WMacii E(2010)Optimizing data-flow graphs with min/max, adding and relational operationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871253(1361-1364)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871253
Gomez-Prado DRen QCiesielski MGuillot JBoutillon EBenini LDe Micheli GAl-Hashimi BMueller W(2009)Optimizing data flow graphs to minimize hardware implementationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874649(117-122)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874649
Ciesielski MAskar SGomez-Prado DGuillot JBoutillon ELauwereins RMadsen J(2007)Data-flow transformations using Taylor expansion diagramsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266463(455-460)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266463
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DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

March 2006

1390 pages

ISBN:3981080106

General Chair:
Georges Gielen
KU Leuven, BE

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European Design and Automation Association

Leuven, Belgium

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Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Pérez JSánchez PFernández VDe Micheli GAl-Hashimi BMueller WMacii E(2010)Optimizing data-flow graphs with min/max, adding and relational operationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871253(1361-1364)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871253
Gomez-Prado DRen QCiesielski MGuillot JBoutillon EBenini LDe Micheli GAl-Hashimi BMueller W(2009)Optimizing data flow graphs to minimize hardware implementationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874649(117-122)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874649
Ciesielski MAskar SGomez-Prado DGuillot JBoutillon ELauwereins RMadsen J(2007)Data-flow transformations using Taylor expansion diagramsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266463(455-460)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266463
Ciesielski MKalla PAskar S(2006)Taylor Expansion DiagramsIEEE Transactions on Computers10.1109/TC.2006.15355:9(1188-1201)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TC.2006.153

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Taylor Expansion Diagrams: a New Representation for RTL Verification

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

High-Level Dataflow Transformations Using Taylor Expansion Diagrams

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Taylor Expansion Diagrams: a New Representation for RTL Verification

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

High-Level Dataflow Transformations Using Taylor Expansion Diagrams

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