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Low power synthesis of dynamic logic circuits using fine-grained clock gating

Published: 06 March 2006 Publication History

Abstract

Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodology for reducing clock power in the active mode for dynamic circuits with fine-grained clock gating. The proposed technique also improves switching power by preventing redundant computations. A logic synthesis approach for domino/skewed logic styles based on Shannon expansion is proposed, that dynamically identifies idle parts of logic and applies clock gating to them to reduce power in the active mode of operation. Results on a set of MCNC benchmark circuits in predictive 70nm process exhibit improvements of 15% to 64% in total power with minimal overhead in terms of delay and area compared to conventionally synthesized domino/skewed logic.

References

[1]
J. Rabaey et. al., Digital Integrated Circuits, 2nd Edition, Prentice Hall.]]
[2]
A. Solomatnikov et. al., Skewed CMOS: noise-tolerant high-performance low-power static circuit family, IEEE TVLSI, Vol. 10, pp. 469--476, 2002.]]
[3]
A. Cao et. al., Synthesis of skewed logic circuits, ACM TODAES, Vol. 10, pp. 205--228, 2004.]]
[4]
H. Li et. al., DCG: Deterministic clock-gating for low-power microprocessor design, IEEE TVLSI, Vol. 12, pp. 245--254, 2004.]]
[5]
P. Babighian et. al., A scalable algorithm for RTL insertion of gated clocks based on ODCs computation, IEEE TCAD, Vol. 24, pp. 29--42, 2005.]]
[6]
R. Krishnarnurthy et. al., High-performance and low-power challenges for sub-70 nm microprocessor circuits, CICC, pp. 12--15, 2002.]]
[7]
A. Chandrakasan, Design of High-Performance Microprocessor Circuits, IEEE Press.]]
[8]
S. Bhunia et. al., A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating, DAC, pp. 479--484, 2005.]]
[9]
L. Lava no et. al., Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool, DAC, pp. 254--260, 1995.]]
[10]
Zhao et. al., Technology Mapping Algorithms for domino logic, ACM TODAES, Vol. 7, pp. 306--335, 2002.]]
[11]
SIS, University of California at Berkeley.]]

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Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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  • (2018)ENFIREIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257893325:1(177-188)Online publication date: 29-Dec-2018
  • (2016)ENFIREProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847325(275-275)Online publication date: 21-Feb-2016
  • (2012)Timing Optimization in Sequential Circuit by Exploiting Clock-Gating LogicACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954817:2(1-15)Online publication date: 1-Apr-2012
  • (2008)A novel sequential circuit optimization with clock gating logicProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509515(230-233)Online publication date: 10-Nov-2008

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