A concurrent testing method for NoC switches

ABSTRACT

This paper proposes reuse of on-chip networks for testing switches in Network on Chips (NoCs). The proposed algorithm broadcasts test vectors of switches through the on-chip networks and detects faults by comparing output responses of switches with each other. This algorithm alleviates the need for: (1) external comparison of the output response of the circuit-under-test with the response of a fault free circuit stored on a tester (2) on-chip signature analysis (3) a dedicated test-bus to reach test vectors and collect their responses. Experimental results on a few test benches compare the proposed algorithm with traditional System on Chip (SoC) test methods.

REFERENCES

• 1: Don Edenfeld , Andrew B. Kahng , Mike Rodgers , Yervant Zorian, 2003 Technology Roadmap for Semiconductors, Computer, v.37 n.1, p.47-56, January 2004 [doi>10.1109/MC.2004.1260725]
• 2: D. Bertozzi and L. Benini, "Xpipes: a network-on-chip architecture for gigascale systems-on-chip," IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18--31, 2004.
• 3: Andrea Bona , Vittorio Zaccaria , Roberto Zafalon, System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip, Proceedings of the conference on Design, automation and test in Europe, p.30318, February 16-20, 2004
• 4: Yervant Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, Proceedings of the IEEE International Test Conference, p.191-199, November 03-05, 1997
• 5: T. J. Chakraborty, S. Bhawmik and C.-H. Chiang, "Test access methodology for system-on-chip testing," Proc. of International TECSWorkshop, pp. 111--117, 2000.
• 6: Vikram Iyengar , Krishnendu Chakrabarty , Mark D. Krasniewski , Gopind N. Kumar, Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs, Proceedings of the 21st IEEE VLSI Test Symposium, p.299, April 27-May 01, 2003
• 7: M. Nahvi and A. Ivanov, "Indirect test architecture for SoC testing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, vo. 7, pp. 1128--1142, 2004.
• 8: B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas, "Bringing communication networks on a chip: test and verification implications," IEEE Communications Magazine, vol. 41, no.9, pp. 74--81, 2003.
• 9: E. Cota, L. Carro, F. Wagner, and M. Lubaszewski, "Power-aware NoC reuse on the testing of core-based systems," Proc. of International Test Conference, pp. 612--621, 2003.
• 10: Érika Cota , Luigi Carro , Marcelo Lubaszewski, Reusing an on-chip network for the test of core-based systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.471-499, October 2004 [doi>10.1145/1027084.1027088]
• 11: Indradeep Ghosh , Niraj K. Jha , Sujit Dey, A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems, Proceedings of the IEEE International Test Conference, p.50-59, November 03-05, 1997
• 12: M. Nourani , C. A. Papachristou, Structural Fault Testing of Embedded Cores Using Pipelining, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.129-144, August-October 1999
• 13: E. Cota , L. Carro , M. Lubaszewski , A. Orailoglu, Test Planning and Design Space Exploration in a Core-Based Environment, Proceedings of the conference on Design, automation and test in Europe, p.478, March 04-08, 2002
• 14: E. Cota , M. Kreutz , C. A. Zeferino , L. Carro , M. Lubaszewski , A. Susin, The Impact of NoC Reuse on the Testing of Core-based Systems, Proceedings of the 21st IEEE VLSI Test Symposium, p.128, April 27-May 01, 2003
• 15: Érika Cota , Luigi Carro , Marcelo Lubaszewski, Reusing an on-chip network for the test of core-based systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.471-499, October 2004 [doi>10.1145/1027084.1027088]
• 16: K. Jong-Sun et al., "On-chip network based embedded core testing," Proc. of IEEE International SOC Conference, pp. 223--226, 2004.
• 17: Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
• 18: Yogen K. Dalal , Robert M. Metcalfe, Reverse path forwarding of broadcast packets, Communications of the ACM, v.21 n.12, p.1040-1048, Dec. 1978 [doi>10.1145/359657.359665]
• 19: H. K. Lee and D. S. Ha, "On the generation of test patterns for combinational circuits," Tech. Rep. 12--93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University, 1993.
• 20: Antoine Jalabert , Srinivasan Murali , Luca Benini , Giovanni De Micheli, ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20884, February 16-20, 2004