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Layout driven data communication optimization for high level synthesis

Published: 06 March 2006 Publication History

Abstract

High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan.

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Cited By

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  • (2007)Compatibility path based binding algorithm for interconnect reduction in high level synthesisProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326164(435-441)Online publication date: 5-Nov-2007

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Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2007)Compatibility path based binding algorithm for interconnect reduction in high level synthesisProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326164(435-441)Online publication date: 5-Nov-2007

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