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ABSTRACT
As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
|
| |
3
|
|
| |
4
|
|
| |
5
|
|
| |
6
|
|
| |
7
|
|
| |
8
|
|
| |
9
|
|
| |
10
|
Dong-Yuan Chen , Lixia Liu , Chen Fu , Shuxin Yang , Chengyong Wu , Roy Ju, Efficient Resource Management during Instruction Scheduling for the EPIC Architecture, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.36, September 27-October 01, 2003
|
| |
11
|
J. Deeney. Thermal modeling and measurement of large high-power silicon devices with asymmetric power distribution. In Proceedings of the 35th International Symposium on Microelectronics, 2002.
|
| |
12
|
E.M.C. Filho, E.S.T. Fernandes, and A. Wolfe. Load balancing in superscalar architectures. In Proceedings of the 22nd EUROMICRO Conference, pp. 651--658, 1996.
|
| |
13
|
A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478--490, 1981.
|
| |
14
|
S. Ghiasi, J. Casmira, D. Grunwald. Using IPC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexity-Effective Design, 2000.
|
| |
15
|
S.H. Gunther, F. Binns, D.M. Carmean, and J.C. Hall. Managing the impact of increasing microprocessor power consumption. Intel Technology Journal, Q1, 2001.
|
| |
16
|
|
| |
17
|
Y. Han, I. Koren, and C. A. Moritz. Temperature aware floorplanning. In Proceedings of the 2nd Workshop on Temperature Aware Computer Systems, 2005.
|
 |
18
|
|
 |
19
|
Michael Huang , Jose Renau , Seung-Moon Yoo , Josep Torrellas, A framework for dynamic energy efficiency and temperature management, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.202-213, December 2000, Monterey, California, United States
[doi> 10.1145/360128.360149]
|
| |
20
|
Wen-Mei W. Hwu , Scott A. Mahlke , William Y. Chen , Pohua P. Chang , Nancy J. Warter , Roger A. Bringmann , Roland G. Ouellette , Richard E. Hank , Tokuzo Kiyohara , Grant E. Haab , John G. Holm , Daniel M. Lavery, The superblock: an effective technique for VLIW and superscalar compilation, The Journal of Supercomputing, v.7 n.1-2, p.229-248, May 1993
[doi> 10.1007/BF01205185]
|
 |
21
|
H. S. Kim , N. Vijaykrishnan , M. Kandemir , M. J. Irwin, Adapting instruction level parallelism for optimizing leakage in VLIW architectures, Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems, June 11-13, 2003, San Diego, California, USA
|
| |
22
|
|
 |
23
|
|
 |
24
|
Scott A. Mahlke , David C. Lin , William Y. Chen , Richard E. Hank , Roger A. Bringmann, Effective compiler support for predicated execution using the hyperblock, Proceedings of the 25th annual international symposium on Microarchitecture, p.45-54, December 01-04, 1992, Portland, Oregon, United States
|
 |
25
|
|
| |
26
|
|
 |
27
|
|
| |
28
|
|
| |
29
|
D. C. Pham. The design and implementation of a first-generation CELL Processor: A multi-core supercomputer SoC. In Proceedings of International Forum on Application Specific MPSoC, 2005.
|
| |
30
|
|
| |
31
|
|
 |
32
|
Kevin Skadron , Mircea R. Stan , Karthik Sankaranarayanan , Wei Huang , Sivakumar Velusamy , David Tarjan, Temperature-aware microarchitecture: Modeling and implementation, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.1, p.94-125, March 2004
[doi> 10.1145/980152.980157]
|
 |
33
|
Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-aware microarchitecture, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
|
 |
34
|
|
| |
35
|
M. C. Toburen, T. M. Conte, and M. Reilly. Instruction Scheduling for Low Power Dissipation in High Performance Microprocessors. In Proceedings of the Power Driven Microarchitecture Workshop, 1998.
|
| |
36
|
|
| |
37
|
Y-F. Tsai, A. Hegde, N. Vijaykrishnan, and M. J. Irwin. ChipPower: An Architecture-Level Leakage Simulator. In Proceedings of IEEE International SoC Conference, pp. 395--398, 2004.
|
| |
38
|
R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur. Thermal performance challenges from silicon to systems. Intel Technology Journal, Q3, 2000.
|
| |
39
|
W. Zhang , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , D. Duarte , Y-F. Tsai, Exploiting VLIW schedule slacks for dynamic and leakage energy reduction, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
|
|