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Compiler-directed thermal management for VLIW functional units
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Source Language, Compiler and Tool Support for Embedded Systems archive
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems table of contents
Ottawa, Ontario, Canada
SESSION: Low power issues table of contents
Pages: 163 - 172  
Year of Publication: 2006
ISBN:1-59593-362-X
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Authors
Madhu Mutyam  International Institute of Information Technology, Hyderabad, India
Feihui Li  The Pennsylvania State University
Vijaykrishnan Narayanan  The Pennsylvania State University
Mahmut Kandemir  The Pennsylvania State University
Mary Jane Irwin  The Pennsylvania State University
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.


REFERENCES

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J. Deeney. Thermal modeling and measurement of large high-power silicon devices with asymmetric power distribution. In Proceedings of the 35th International Symposium on Microelectronics, 2002.
 
12
E.M.C. Filho, E.S.T. Fernandes, and A. Wolfe. Load balancing in superscalar architectures. In Proceedings of the 22nd EUROMICRO Conference, pp. 651--658, 1996.
 
13
A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478--490, 1981.
 
14
S. Ghiasi, J. Casmira, D. Grunwald. Using IPC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexity-Effective Design, 2000.
 
15
S.H. Gunther, F. Binns, D.M. Carmean, and J.C. Hall. Managing the impact of increasing microprocessor power consumption. Intel Technology Journal, Q1, 2001.
 
16
 
17
Y. Han, I. Koren, and C. A. Moritz. Temperature aware floorplanning. In Proceedings of the 2nd Workshop on Temperature Aware Computer Systems, 2005.
18
19
 
20
21
 
22
23
24
25
 
26
27
 
28
 
29
D. C. Pham. The design and implementation of a first-generation CELL Processor: A multi-core supercomputer SoC. In Proceedings of International Forum on Application Specific MPSoC, 2005.
 
30
 
31
32
33
34
 
35
M. C. Toburen, T. M. Conte, and M. Reilly. Instruction Scheduling for Low Power Dissipation in High Performance Microprocessors. In Proceedings of the Power Driven Microarchitecture Workshop, 1998.
 
36
 
37
Y-F. Tsai, A. Hegde, N. Vijaykrishnan, and M. J. Irwin. ChipPower: An Architecture-Level Leakage Simulator. In Proceedings of IEEE International SoC Conference, pp. 395--398, 2004.
 
38
R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur. Thermal performance challenges from silicon to systems. Intel Technology Journal, Q3, 2000.
 
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Collaborative Colleagues:
Madhu Mutyam: colleagues
Feihui Li: colleagues
Vijaykrishnan Narayanan: colleagues
Mahmut Kandemir: colleagues
Mary Jane Irwin: colleagues