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Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications

Published: 23 April 2006 Publication History

Abstract

In this research we investigate an approach for adaptive dynamic instruction set extension, tuning processors to specific applications after fabrication.

References

[1]
Ye, Z. A., Moshovos A., Hauck S., and Banerjee P. Chimaera: a high-performance architecture with tightly-coupled reconfigurable functional unit. In the proceeding of 27th International Symposium of Computer Architecture (ISCA), 2000, pages 225--235.
[2]
http://www.eecs.umich.edu/mibench/
[3]
http://ww.simplescalar.com/

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  1. Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications

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      cover image ACM Conferences
      SAC '06: Proceedings of the 2006 ACM symposium on Applied computing
      April 2006
      1967 pages
      ISBN:1595931082
      DOI:10.1145/1141277
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      Published: 23 April 2006

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      Author Tags

      1. adaptive dynamic processor
      2. custom instruction
      3. hot basic block
      4. instruction set extension
      5. online profiling

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