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The art of multiprocessor programming

Published: 23 July 2006 Publication History

Abstract

Computer architecture is about to undergo, if not another revolution, then a vigorous shaking-up. The major chip manufacturers have, for the time being, simply given up trying to make processors run faster. Instead, they have recently started shipping "multicore" architectures, in which multiple processors (cores) communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed.As a result, system designers and software engineers can no longer rely on increasing clock speed to hide software bloat. Instead, they must somehow learn to make effective use of increasing parallelism. This adaptation will not be easy. Conventional synchronization techniques based on locks and conditions are unlikely to be effective in such a demanding environment. Coarse-grained locks, which protect relatively large amounts of data, do not scale, and fine-grained locks introduce substantial software engineering problem.Transactional memory is a computational model in which threads synchronize by optimistic, lock-free transactions. This synchronization model promises to alleviate many (not all) of the problems associated with locking, and there is a growing community of researchers working on both software and hardware support for this approach. This talk will survey the area, with a focus on open research problems.

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cover image ACM Conferences
PODC '06: Proceedings of the twenty-fifth annual ACM symposium on Principles of distributed computing
July 2006
230 pages
ISBN:1595933840
DOI:10.1145/1146381
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2006

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Overall Acceptance Rate 740 of 2,477 submissions, 30%

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  • (2024)Hardware and Software Co-Design for Optimized Decoding Schemes and Application Mapping in NVM Compute-in-Memory ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344721643:11(3744-3755)Online publication date: Nov-2024
  • (2024)The Impact of Asynchrony on Stability of MAC2024 IEEE 44th International Conference on Distributed Computing Systems (ICDCS)10.1109/ICDCS60910.2024.00023(151-162)Online publication date: 23-Jul-2024
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  • (2019)Cost Evaluation of Synchronization Algorithms for Multicore ArchitecturesAdvanced Methodologies and Technologies in Network Architecture, Mobile Computing, and Data Analytics10.4018/978-1-5225-7598-6.ch051(697-713)Online publication date: 2019
  • (2018)Cost Evaluation of Synchronization Algorithms for Multicore ArchitecturesEncyclopedia of Information Science and Technology, Fourth Edition10.4018/978-1-5225-2255-3.ch346(3989-4003)Online publication date: 2018
  • (2017)A Collision-Mitigation Cuckoo Hashing Scheme for Large-Scale Storage SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.259476328:3(619-632)Online publication date: 1-Mar-2017
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