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Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual conference on Design automation table of contents
San Francisco, CA, USA
SESSION: Session 5: practical applications of DFM table of contents
Pages: 69 - 72  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Rouwaida Kanj  IBM Austin Research Labs, Austin, TX
Rajiv Joshi  IBM TJ Watson Labs, Yorktown Heights, NY
Sani Nassif  IBM Austin Research Labs, Austin, TX
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 12,   Downloads (12 Months): 95,   Citation Count: 8
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ABSTRACT

In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100X compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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D. E. Hocevar, M. R. Lightner, and T. N. Trick, "A Study of Variance Reduction Techniques for Estimating Circuit Yields", IEEE Trans. on CAD, vol. 2, no. 3, pp. 180--192, July 1983.
 
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R. V. Joshi et al., "Variability analysis for Sub-100 nm PD/SOI CMOS SRAM cell", Proc. of the 30th ESSCC, 2004, pp. 211--214.
 
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W. G. Cochran, Sampling Techniques, 3rd edition. New York: Wiley, 1977.
 
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T. C. Hesterberg, "Advances in importance sampling", Ph.D. Dissertation, Statistics Department, Stanford University, 1988.
 
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D.S. Gibson, R. Poddar, G. S. May, M. A. Brooke, "Statistically based parametric yield prediction for integrated circuits", IEEE Trans. on Semiconductor Manufacturing, vol. 10, no. 4, pp.445--458 Nov. 1997.
 
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G. Schueller, H. Pradlewarter, and P. S. Koutsourelakis, "A comparative study of reliability estimation procedures for high dimensions", 16th ASCE Engineering mechanics conference, 2003.
 
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A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE JSSC, vol. 36, no. 4, pp. 658--665, April 2001.
 
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CITED BY  8
 
 
 
 
 
 

Collaborative Colleagues:
Rouwaida Kanj: colleagues
Rajiv Joshi: colleagues
Sani Nassif: colleagues