Challenges in sleep transistor design and implementation in low-power designs

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Challenges in sleep transistor design and implementation in low-power designs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual conference on Design automation table of contents

San Francisco, CA, USA

SESSION: Session 8: leakage, power analysis and optimization table of contents

Pages: 113 - 116

Year of Publication: 2006

ISBN:1-59593-381-6

Authors

Kaijian Shi	Synopsys Inc., Dallas, TX
David Howard	ARM Ltd., Cambridge, UK

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 78, Citation Count: 5

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ABSTRACT

Optimum power gating sleep transistor design and implementation are critical to a successful low-power design. This paper describes important considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. It also investigated various power-on current rush control methods for the sleep transistor implementation.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kaushik Roy, Saibal Mukhopadhyay, and Hamid Mahmoodi-meimand, "Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits", Proc. IEEE Vol. 91, no. 2, Feb. 2003
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	7	Anand Ramalingam , Bin Zhang , Anirudh Devgan , David Z. Pan, Sleep transistor sizing using timing criticality and temporal currents, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120832]

CITED BY 5

	Shi-Hao Chen , Jiing-Yuan Lin, Experiences of low power design implementation and verification, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Yu-Ting Chen , Da-Cheng Juan , Ming-Chao Lee , Shih-Chieh Chang, An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Liangpeng Guo , Yici Cai , Qiang Zhou , Le Kang , Xianlong Hong, A novel performance driven power gating based on distributed sleep transistor network, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	De-Shiuan Chiou , Da-Cheng Juan , Yu-Ting Chen , Shih-Chieh Chang, Fine-grained sleep transistor sizing algorithm for leakage power minimization, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Hamed F. Dadgour , Kaustav Banerjee, Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California