| Model order reduction of linear networks with massive ports via frequency-dependent port packing |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 43rd annual conference on Design automation
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San Francisco, CA, USA
SESSION: Session 15: gate modeling and model order reduction
table of contents
Pages: 267 - 272
Year of Publication: 2006
ISBN:1-59593-381-6
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Authors
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Peng Li
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Texas A&M University, College Station, TX
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Weiping Shi
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Texas A&M University, College Station, TX
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Downloads (6 Weeks): 4, Downloads (12 Months): 24, Citation Count: 1
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ABSTRACT
Model order reduction has been a driving force for reducing analysis complexity of VLSI systems containing large linear networks. However, most existing reduction techniques are only applicable to networks with a small number of ports, failing to fulfill an even stronger need of reducing massively interconnected subsystems such as power grids and wide buses. In this paper, a port packing scheme is presented wherein the correlation between circuit ports is explored in a frequency-dependent manner. In the proposed McPack Multiport Circuit Packing) algorithm, port packing is combined with a practical realization of the recently developed tangential interpolation scheme for model reduction. McPack performs feasible moment matching for networks with many ports in the sense of tangential interpolation. With guaranteed passivity, extensibility to multi-point expansion as well as comparable complexity, McPack systematically introduces frequency-domain port packing into the existing projection-based model order reduction framework. For several large networks with high port count, the presented algorithm is shown to be significantly more accurate than the standard block-moment matching algorithm as well as other recently developed alternative.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY
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Xiaoji Ye , Peng Li , Min Zhao , Rajendran Panda , Jiang Hu, Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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