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Fast algorithms for slew constrained minimum cost buffering
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual conference on Design automation table of contents
San Francisco, CA, USA
SESSION: Session 18: buffer insertion table of contents
Pages: 308 - 313  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Shiyan Hu  Texas A&M University, College Station, TX
Charles J. Alpert  IBM Austin Research, Austin, TX
Jiang Hu  Texas A&M University, College Station, TX
Shrirang Karandikar  IBM Austin Research, Austin, TX
Zhuo Li  Texas A&M University, College Station, TX
Weiping Shi  Texas A&M University, College Station, TX
C. N. Sze  IBM Austin Research, Austin, TX
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 7,   Downloads (12 Months): 28,   Citation Count: 4
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ABSTRACT

As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techniques to handle large volume of nets, while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve > 100X speed up and save up to 40% buffer area over the commonly-used van Ginneken style buffering.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Saxena and N. Menezes and P. Cocchini and D. A. Kirkpatrick, "Repeater scaling and its impact on CAD," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 4, pp. 451--463, 2004.
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J. Lillis and C.-K. Cheng and T.-T.Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Journal of Solid State Circuits, vol. 31, no. 3, pp. 437--447, 1996.
 
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H. B. Bakoglu, Circuits, Interconnects, and Packaging for Addison-Wesley Publishing Company, 1990.
 
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N. H. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Addison Wesley, 1993, pp. 221--223.
 
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L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865--868, 1990.


Collaborative Colleagues:
Shiyan Hu: colleagues
Charles J. Alpert: colleagues
Jiang Hu: colleagues
Shrirang Karandikar: colleagues
Zhuo Li: colleagues
Weiping Shi: colleagues
C. N. Sze: colleagues