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A test pattern ordering algorithm for diagnosis with truncated fail data
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 43rd annual conference on Design automation table of contents
San Francisco, CA, USA
SESSION: Session 25: the test bin table of contents
Pages: 399 - 404  
Year of Publication: 2006
ISBN:1-59593-381-6
Authors
Gang Chen  Mentor Graphics Corp., Wilsonville, OR
Sudhakar M. Reddy  University of Iowa, Iowa City, IA
Irith Pomeranz  Purdue University, W. Lafayette, IN
Janusz Rajski  Mentor Graphics Corp., Wilsonville, OR
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. Radojcic and M. Rencher, "Old Rules No Longer Apply", EETimes, April 2003.
 
2
 
3
 
4
B. Chess, T. Larrabee, "Creating Small Fault Dictionaries", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, iss. 3, pp. 346--356, 1999.
 
5
 
6
 
7
 
8
P. Camurati, et. al., "A Diagnostic Test Pattern Generation Algorithm", ITC, pp. 52--58, 1990.
 
9
 
10
 
11
 
12
 
13
 
14
 
15
S. K. Goel and E. J. Marinissen, "Optimisation of On-chip Design-for-test Infrastructure for Maximal Multi-site Test Throughput", IEE Proc. On Computer and Digital Techniques, pp. 442--456, vol. 152, no. 3, 2005.
 
16
V. Dabholkar, S. Chakravarty, I. Pomeranz, S. Reddy, "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application", IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp. 1325--1333, vol. 17, no. 12, 1998.
 
17
 
18
P. Girard, C. Landrault, S. Pravossoudovitch, D. Severac, "Reduction of Power Consumption During Test Application by Test Vector Ordering", IEE Electronic Letters, pp. 1752--1754, vol. 33, no. 21, 1997.
 
19
P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Power Profile Manipulation: a New Approach for Reducing Test Application Time under Power Constraints:, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp. 1217--1225, vol. 21, no. 10, 2002.

Collaborative Colleagues:
Gang Chen: colleagues
Sudhakar M. Reddy: colleagues
Irith Pomeranz: colleagues
Janusz Rajski: colleagues