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A PLA based asynchronous micropipelining approach for subthreshold circuit design

Published: 24 July 2006 Publication History

Abstract

Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7x, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4x, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well.

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  • (2017)A Robust C-element Design with Enhanced Metastability PerformanceProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060425(95-100)Online publication date: 10-May-2017
  • (2015)Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAsProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742120(111-114)Online publication date: 20-May-2015
  • (2014)Look-up Table Design for Deep Sub-threshold through Full-Supply Operation2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2014.80(259-266)Online publication date: May-2014
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    cover image ACM Conferences
    DAC '06: Proceedings of the 43rd annual Design Automation Conference
    July 2006
    1166 pages
    ISBN:1595933816
    DOI:10.1145/1146909
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 24 July 2006

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    Author Tags

    1. PLA
    2. asynchronous
    3. micro-pipelining
    4. sub-threshold

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    Cited By

    View all
    • (2017)A Robust C-element Design with Enhanced Metastability PerformanceProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060425(95-100)Online publication date: 10-May-2017
    • (2015)Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAsProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742120(111-114)Online publication date: 20-May-2015
    • (2014)Look-up Table Design for Deep Sub-threshold through Full-Supply Operation2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2014.80(259-266)Online publication date: May-2014
    • (2013)Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper controlProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648735(267-272)Online publication date: 4-Sep-2013
    • (2013)Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper controlInternational Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2013.6629307(267-272)Online publication date: Sep-2013
    • (2013)Soft MOUSETRAPProceedings of the 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems10.1109/ASYNC.2013.29(1-7)Online publication date: 19-May-2013
    • (2010)Digital Subthreshold for Ultra-Low Power Operation: Prospects and ChallengesLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_6(185-207)Online publication date: 25-Oct-2010
    • (2009)3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413111(498-504)Online publication date: Oct-2009
    • (2009)Design of the ChipMinimizing and Exploiting Leakage in VLSI Design10.1007/978-1-4419-0950-3_14(163-175)Online publication date: 20-Oct-2009
    • (2009)3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital CircuitsAnalysis and Design of Resilient VLSI Circuits10.1007/978-1-4419-0931-2_5(71-86)Online publication date: 21-Sep-2009
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