A PLA based asynchronous micropipelining approach for subthreshold circuit design

ABSTRACT

Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7x, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4x, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well.

REFERENCES

• 1: "The International Technology Roadmap for Semiconductors."http://public.itrs.net/, 2003.
• 2: W. Daasch, C. Lim, and G. Cai, "Design of vlsi cmos circuits under thermal constraint," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, pp. 589--593, Aug 2002.
• 3: S.-H. Choi, B.-K. Kim, J. Park, C.-H. Kang, and D.-S. Eom, "An implementation of wireless sensor network," IEEE Transactions on Consumer Electronics, vol. 50, pp. 236--244, Feb 2004.
• 4: "The MultimodAl NeTworks of In-situ Sensors (MANTIS) project." http://mantis.cs.colorado.edu, 2004.
• 5: A. Abidi, G. Pottie, and W. Kaiser, "Power-conscious design of wireless circuits and systems," Proceedings of the IEEE, vol. 88, pp. 1528--1545, Oct 2000.
• 6: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 7: Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
• 8: Hendrawan Soeleman , Kaushik Roy , Bipul C. Paul, Robust subthreshold logic for ultra-low power operation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.1, p.90-100, Feb. 2001 [doi>10.1109/92.920822 ]
• 9: Hendrawan Soeleman , Kaushik Roy, Digital CMOS logic operation in the sub-threshold region, Proceedings of the 10th Great Lakes symposium on VLSI, p.107-112, March 02-04, 2000, Chicago, Illinois, United States [doi>10.1145/330855.331014]
• 10: Hendrawan Soeleman , Kaushik Roy, Ultra-low power digital subthreshold logic circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.94-96, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313874]
• 11: Nikhil Jayakumar , Sunil P. Khatri, A variation tolerant subthreshold design approach, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA [doi>10.1145/1065579.1065767]
• 12: Man L. Mui , Kaustav Banerjee , Amit Mehrotra, Power Supply Optimization in sub-130 nm Leakage Dominant Technologies, Proceedings of the 5th International Symposium on Quality Electronic Design, p.409-414, March 22-24, 2004
• 13: K. Kanda, K. Nose, K. Kawaguchi, and T. Sakurai, "Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs,"IEEE Journal of Solid-State Circuits, vol. 36, p. 1559=1564, Oct 2001.
• 14: Nikhil Jayakumar , Sunil P. Khatri, Minimum Energy Near-threshold Network of PLA based Design, Proceedings of the 2005 International Conference on Computer Design, p.399-404, October 02-05, 2005 [doi>10.1109/ICCD.2005.75]
• 15: B. Paul, H. Soeleman, and K. Roy, "An 8x8 sub-threshold digital CMOS carry save array multiplier," in European Solid State Circuits Conference, Sept 2001.
• 16: S. P. Khatri, Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics. PhD thesis, UC Berkeley, Dec 1999.
• 17: S. Khatri, R. Brayton, and A. Sangiovanni-Vincentelli, "A VLSI design methodology using a network of PLAs embedded in a regular layout fabric," Tech. Rep. UCB/ERL M99/50, Electronics Research Laboratory, University of California, Berkeley, May 1999.
• 18: Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
• 19: E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERLM92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.
• 20: Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. of IEEE Custom Integrated Circuit Conference, pp. 201--204, Jun 2000. http://www-device.eecs.berkeley.edu/~ptm.
• 21: F. Mo and R. Brayton, "PLA-based regular structures and their synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 723--729, June 2003.
• 22: Fan Mo , Robert K. Brayton, River PLAs: a regular circuit structure, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513970]
• 23: Fan Mo , Robert K. Brayton, Whirlpool PLAs: a regular logic structure and their synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.543-550, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774652]
• 24: L. Nagel, "Spice: A computer program to simulate computer circuits," inUniversity of California, Berkeley UCB/ERL Memo M520, May 1995.
• 25: R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power cmos," IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210--1216, 1997.
• 26: A. Wang, A. Chandrakasan, and S. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits," Proceedings, IEEE Computer Society Annual Symposium on VLSI, pp. 5--9, Apr 2003.
• 27: B. H. Calhoun, A. Wang, A. Chandrakasan, and S. Kosonocky, "Device sizing for minimum energy operation in subthreshold circuits," Proceedings, IEEE Custom Integrated Circuits Conference, pp. 95--98, Oct 2004.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design

Keywords:
PLA, asynchronous, micro-pipelining, sub-threshold