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IMPRES: integrated monitoring for processor reliability and security

Published: 24 July 2006 Publication History

Abstract

Security and reliability in processor based systems are concernsrequiring adroit solutions.Securityis often compromised by code injection attacks, jeopardizing even `trusted software'.Reliabilityis of concern where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increasecodesize by large amounts and therefore significantly reduce performance. Hardware assisted approaches add extensive amountsofhardware monitors and thus incur unacceptably highhardware cost. This paper presents a novel hardware/softwaretechniqueat the granularity of micro-instructions to reduce overheads considerably. Experiments show thatour technique incurs an additional hardware overhead of 0.91% and clock period increase of 0.06%. Average clock cycle and code size overheads are just 11.9% and 10.6% forfive industrystandard application benchmarks. These overheads are far smaller than have been previously encountered.

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      cover image ACM Conferences
      DAC '06: Proceedings of the 43rd annual Design Automation Conference
      July 2006
      1166 pages
      ISBN:1595933816
      DOI:10.1145/1146909
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 24 July 2006

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      Author Tags

      1. basic block checksumming
      2. bit flips detection
      3. check sum encryption
      4. detecting code injection attacks

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      DAC06: The 43rd Annual Design Automation Conference 2006
      July 24 - 28, 2006
      CA, San Francisco, USA

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      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      Cited By

      View all
      • (2023)MarCNNet: A Markovian Convolutional Neural Network for Malware Detection and Monitoring Multi-Core SystemsIEEE Transactions on Computers10.1109/TC.2022.318452072:4(1122-1135)Online publication date: 1-Apr-2023
      • (2023)Intrusion Injection for Virtualized Systems: Concepts and Approach2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN58367.2023.00047(417-430)Online publication date: Jun-2023
      • (2022)Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC57363.2022.00052(284-290)Online publication date: Dec-2022
      • (2019)Adaptive security monitoring for next-generation routersEURASIP Journal on Embedded Systems10.1186/s13639-018-0087-02019:1Online publication date: 10-Jan-2019
      • (2019)Securing IoT Protocol Implementations Through Hardware Monitoring2019 IEEE 16th International Conference on Mobile Ad Hoc and Sensor Systems (MASS)10.1109/MASS.2019.00061(467-475)Online publication date: Nov-2019
      • (2018)Hardware-assisted integrity monitor based on lightweight hash functionIEICE Electronics Express10.1587/elex.15.2018010715:10(20180107-20180107)Online publication date: 2018
      • (2018)An efficient control flow validation method using redundant computing capacity of dual-processor architecturePLOS ONE10.1371/journal.pone.020112713:8(e0201127)Online publication date: 1-Aug-2018
      • (2018)Can Soft Errors be Handled Securely?2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00032(124-129)Online publication date: Jul-2018
      • (2018)Investigating Reliability and Security of Integrated Circuits and Systems2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00029(106-111)Online publication date: Jul-2018
      • (2018)An Efficient Checkpoint and Recovery Mechanism for Real-Time Embedded Systems2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)10.1109/BDCloud.2018.00123(824-831)Online publication date: Dec-2018
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