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Leakage power reduction of embedded memories on FPGAs through location assignment

Published: 24 July 2006 Publication History

Abstract

Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already have a significant amount of memory on the die, and with each generation the proportion of embedded memory to logic cells is growing. While assigning high Vth can limit the leakage power, embedded memory timing is critical to performance and will draw an increasingly significant amount of leakage current. However, unlike in many processor based systems, on-chip memory accesses are often fully deterministic and completely under the control of the scheduler. In this paper we explore a variety of techniques to battle the problem of leakage in FPGA embedded memories that range in complexity and effectiveness. Through the addition of sleep and drowsy modes, controlled by the scheduler, the amount of leakage power can be reduced by several orders of magnitude. We show how even very simple schemes offer large amounts of benefit, and that further reductions are possible through careful leakage-aware data placement.

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Cited By

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  • (2017)Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA ArchitectureField - Programmable Gate Array10.5772/67257Online publication date: 31-May-2017
  • (2017)An Overview on Memristor-Based Non-volatile LUT of an FPGAFrontiers in Electronic Technologies10.1007/978-981-10-4235-5_8(117-132)Online publication date: 24-Mar-2017
  • (2012)RRAM-based FPGA for "normally off, instantly on" applicationsProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765510(101-108)Online publication date: 4-Jul-2012
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cover image ACM Conferences
DAC '06: Proceedings of the 43rd annual Design Automation Conference
July 2006
1166 pages
ISBN:1595933816
DOI:10.1145/1146909
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 July 2006

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Author Tags

  1. embedded memory
  2. leakage power
  3. location assignment

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DAC06
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DAC06: The 43rd Annual Design Automation Conference 2006
July 24 - 28, 2006
CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2017)Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA ArchitectureField - Programmable Gate Array10.5772/67257Online publication date: 31-May-2017
  • (2017)An Overview on Memristor-Based Non-volatile LUT of an FPGAFrontiers in Electronic Technologies10.1007/978-981-10-4235-5_8(117-132)Online publication date: 24-Mar-2017
  • (2012)RRAM-based FPGA for "normally off, instantly on" applicationsProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765510(101-108)Online publication date: 4-Jul-2012
  • (2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950944(661-667)Online publication date: 25-Jan-2011
  • (2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722270(661-667)Online publication date: Jan-2011
  • (2009)Leakage-aware task scheduling for partially dynamically reconfigurable FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1562514.156252014:4(1-26)Online publication date: 28-Aug-2009
  • (2009)Rotation Scheduling and Voltage Assignment to Minimize Energy for SoCProceedings of the 2009 International Conference on Computational Science and Engineering - Volume 0210.1109/CSE.2009.153(48-55)Online publication date: 29-Aug-2009
  • (2008)Design space exploration of a cooperative MIMO receiver for reconfigurable architecturesProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580173(167-172)Online publication date: 2-Jul-2008
  • (2007)Post-placement leakage optimization for partially dynamically reconfigurable FPGAsProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283801(92-97)Online publication date: 27-Aug-2007

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