Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

ABSTRACT

We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a normally distributed random variable. The resulting synthesis problem is relaxed to the convex quadratic optimization problem and is solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By varying the value of timing yield constraint, a trade-off between minimization of buses and energy reduction is explored. The experimental results show the significant reduction of communication energy with the increasing timing yield. However, the timing yield offers a limitation to minimize the size of bus width and number of buses, if the yield is increased beyond a certain limit.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

General Terms:
Algorithms, Design

Keywords:
communication bus synthesis, voltage scaling