A family of cells to reduce the soft-error-rate in ternary-CAM

ABSTRACT

Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a ternary content-addressable memory (CAM) design with high immunity to SEU. Conventionally, error-correcting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. We propose a family of TCAM cells that reduce the SER at the cost of some area increase. An SER reduction of up to 40% can be obtained with a 18% increase of area; another design reduces the SER by 16% with only a 5% increase in area.

REFERENCES

• 1: Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005 [doi>10.1109/MDT.2005.69]
• 2: Tino Heijmen, Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits, Proceedings of the 11th IEEE International On-Line Testing Symposium, p.3-8, July 06-08, 2005 [doi>10.1109/IOLTS.2005.15]
• 3: Kostas Pagiamtzis and Ali Sheikholeslami. Content-addressable memory (CAM) circuits and architectures: A tutorial and survey. IEEE Journal of Solid-State Circuits, 41(3):712--727, March 2006.
• 4: H.J. Chao. Next generation routers. Proceedings of the IEEE, 90(9):1518--1558, Sept. 2002.
• 5: H. Noda, K. Inoue, M. Kuroiwa, et al. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical search and shift redudancy architecture. Journal of Solid State Circuits, 40(1):245--253, Jan. 2005.
• 6: H. Noda, K. Dosaka, F. Morishita, K. Arimoto, et al. A soft-error immune maintenance-free TCAM architecture with associated embedded DRAM. Custom Integrated Circuits Conf., pages 451--454, Sept. 2005.
• 7: Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler , Doug Burger , Lorenzo Alvisi, Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Proceedings of the 2002 International Conference on Dependable Systems and Networks, p.389-398, June 23-26, 2002
• 8: P. Hazucha and C. Svensson. Impact of CMOS technology scaling on the atmospheric neutron soft error rate. Trans. on Nuclear Science, 47(6):2586--2594, Dec. 2000.
• 9: T. Juhnke and H. Klar. Calculation of the soft error rate of submicron CMOS logic circuits. Journal of Solid-State Circuits, 30(7):830--834, July 1995.
• 10: N. Seifer, D. Moyer, N. Leland, and R. Hokinson. Historical trend in alpha-particle induced soft error rates of the Alpha™ microprocessor. Inter. Reliability Physics Symp., pages 259--265, April 2001.
• 11: http://www-device.eecs.berkeley.edu/~ptm/.
• 12: R. Venkatraman et al. The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications. Transactions on Electron Devices, 52(2):218--226, Feb. 2005.
• 13: L. B. Freeman, Critical charge calculations for a bipolar SRAM array, IBM Journal of Research and Development, v.40 n.1, p.119-129, Jan. 1996
• 14: P.F. Lin and J.B. Kuo. A 0.8-V 128-kb four-wayset-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. Journal of Solid-State Circuits, 37(10):1307--1317, Oct. 2002.
• 15: Navid Azizi , Farid N. Najm, An Asymmetric SRAM Cell to Lower Gate Leakage, Proceedings of the 5th International Symposium on Quality Electronic Design, p.534-539, March 22-24, 2004
• 16: E. Seevinck Sr., F. J. List, and J. Lohstroh. Static-noise margin analysis of MOS SRAM cells. Journal of Solid-State Circuits, 22:748--754, Oct. 1987.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories

General Terms:
Design

Keywords:
content-addressable memory, soft-error rate