Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

ABSTRACT

Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control.

REFERENCES

• 1: K. Roy et. al, Leakage current mechanisms and leakage reduction techniques in Deep-submicron CMOS Circuits, Proc. IEEE, 2003.
• 2: H. Kawaguchi et. al, Dynamic leakage cut-off scheme for low-voltage SRAM's, VLSI Circuits, 1998.
• 3: Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor Mudge, Drowsy caches: simple techniques for reducing leakage power, Proceedings of the 29th annual international symposium on Computer architecture, p.148, May 25-29, 2002, Anchorage, Alaska
• 4: A. J. Bhavnagarwala et. al, Dynamic-threshold CMOS SRAMs for fast, portable applications, ASIC/SOC, 2000.
• 5: Huifang Qin , Yu Cao , Dejan Markovic , Andrei Vladimirescu , Jan Rabaey, SRAM Leakage Suppression by Minimizing Standby Supply Voltage, Proceedings of the 5th International Symposium on Quality Electronic Design, p.55-60, March 22-24, 2004
• 6: A. Bhavnagarwala, et. al., "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," JSCC 2001.
• 7: S. Mukhopadhyay , H. Mahmoodi , K. Roy, Statistical design and optimization of SRAM cell for yield enhancement, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.10-13, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382534]
• 8: BPTM 70nm: Berkeley predictive technology model.
• 9: Yuan Taur , Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, New York, NY, 1998
• 10: Rajeev R. Rao , Anirudh Devgan , David Blaauw , Dennis Sylvester, Parametric yield estimation considering leakage variability, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996693]
• 11: N. C. Beaulieu, et. al, Estimating the distribution of a sum of independent lognormal random variables, TComm, 1995.
• 12: A. Papoulis, Probability, random variables and stochastic process
• 13: M. L. Bushnell et. al., Essentials of electronic testing for digital, memory and mixed-signal VSLI circuits, Kluwer, 2001.
• 14: S. Mukhopadhyay, et. al, Design of reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring, ITC, 2005.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Static memory (SRAM)

General Terms:
Algorithms, Design, Experimentation

Keywords:
adaptive source biasing, hold failures, low power SRAM