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A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Published: 24 July 2006 Publication History

Abstract

Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. In this paper, a novel keeper architecture is proposed which is capable of significantly reducing the contention and improving the performance and power consumption. Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. It is shown that for an 8-input OR gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to traditional keeper circuit.

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Cited By

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  • (2023)Domino circuit design of a Sub-32nm wide FAN-in GATEMPHYSICAL MESOMECHANICS OF CONDENSED MATTER: Physical Principles of Multiscale Structure Formation and the Mechanisms of Nonlinear Behavior: MESO202210.1063/5.0144404(060034)Online publication date: 2023
  • (2017)A high performance dynamic logic with nMOS based resistive keeper circuit2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)10.1109/ISCAIE.2017.8074950(60-64)Online publication date: Apr-2017
  • (2017)A low power dynamic logic with nMOS based resistive keeper circuit2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA)10.1109/ICIMIA.2017.7975597(181-185)Online publication date: Feb-2017
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    cover image ACM Conferences
    DAC '06: Proceedings of the 43rd annual Design Automation Conference
    July 2006
    1166 pages
    ISBN:1595933816
    DOI:10.1145/1146909
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 24 July 2006

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    Author Tags

    1. VLSI
    2. dynamic gates
    3. keeper design
    4. low-power design
    5. process variation
    6. reliability
    7. robustness

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    July 24 - 28, 2006
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    Cited By

    View all
    • (2023)Domino circuit design of a Sub-32nm wide FAN-in GATEMPHYSICAL MESOMECHANICS OF CONDENSED MATTER: Physical Principles of Multiscale Structure Formation and the Mechanisms of Nonlinear Behavior: MESO202210.1063/5.0144404(060034)Online publication date: 2023
    • (2017)A high performance dynamic logic with nMOS based resistive keeper circuit2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)10.1109/ISCAIE.2017.8074950(60-64)Online publication date: Apr-2017
    • (2017)A low power dynamic logic with nMOS based resistive keeper circuit2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA)10.1109/ICIMIA.2017.7975597(181-185)Online publication date: Feb-2017
    • (2015)Controlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logicElectronics Letters10.1049/el.2015.095251:23(1856-1857)Online publication date: Nov-2015
    • (2012)A survey on different keeper design topologies for high speed wide AND-OR domino circuits2012 Students Conference on Engineering and Systems10.1109/SCES.2012.6199055(1-4)Online publication date: Mar-2012
    • (2010)A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic OR gatesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202559118:11(1567-1577)Online publication date: 1-Nov-2010
    • (2009)High-speed low-power FinFET based domino logicProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509818(829-834)Online publication date: 19-Jan-2009
    • (2009)High-speed low-power FinFET based domino logic2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796583(829-834)Online publication date: Jan-2009
    • (2007)Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applicationsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278559(306-311)Online publication date: 4-Jun-2007

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